Native SystemVerilog verification tool from Synopsys
Synopsys has introduced a verification tool written entirely in SystemVerilog, with native support for UVM, VMM and OVM verification methodologies, and a debug environment that is aware of communication protocols.
Called ‘Discovery Verification IP’, it is claimed to be up to 4x faster than the firm’s own DesignWare tool.
“There are two big differences between Discovery and what is available in the field today, and our own DesignWare is very representative of products in the field today,” group marketing manager Neil Mullinger told Electronics Weekly. “Discovery is a 100% SystemVerilog architecture, and it has a protocol-aware debug environment.”
Writing the tool in SystemVerilog means there is no requirement, and therefore no processing overhead, for wrappers or methodology extensions around an original implementation in a different language.
“Discovery VIP is architected with native support for UVM, VMM and OVM without methodology-level interoperability wrappers or under-the-hood translations or remapping,” said Synopsys. “Not only does this remove unnecessary performance overhead, but it also offers portability across all major simulators and easy integration within SoC environments, as well as capabilities and features for VIP debug, coverage planning and management.”
UVM, VMM and OVM are respectively: universal verification methodology, verification methodology manual and open verification methodology.
It provides functional models of on- and off-chip protocols like ARM AMBA, PCI Express, USB, MIPI, HDMI and Ethernet. “Verification engineers use these models to test all SoC interfaces before manufacturing, enabling them to verify whether an interface conforms to published standards,” said Synopsys.
What is protocol-aware debug?
Mullinger gave an example: “What people like about this tool is that in a waveform view in a simulator it can decode the waveform into commands – read – preamble – data – completion – acknowledge,” he said. And beyond this: “With USB3.0 for example, the host might start a read and, before that data is finished, start another write. The transactions are in parallel, and it is hard to understand. Discovery will separate the separate transactions to display them in separate time synchronised columns.” (See image).
It is also possible to display the protocols on either side of an interface.
The complete portfolio of protocols includes: USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, and more), Ethernet 40G/100G, PCI Express, SATA, and OCP.Tags: Synopsys, SystemVerilog, verification