Synopsys gives Freescale verification route for SoCs

Synopsys is working with Freescale Semiconductor on verification of IP blocks for complex system-on-chip (SoC) devices. An aim of the collaboration, said the companies, is to achieve better schedule predictability and lower overall verification costs for complex SoCs.

“Over the last few years, our designs have led a very aggressive roadmap of SoC platforms with considerable verification challenges,” said Ken Hansen, vice president and chief technology officer at Freescale Semiconductor.

“With the increasing use of standards-based IPs, verification challenges shift to finding the fastest and most effective way to validate the integration of complex protocols with our differentiated SoC content, while boosting debug and simulation performance,” said Hansen.

The design tool firm’s simulation and verification IP portfolio provides UVM support, and advanced debug capabilities.

“This strategic collaboration with Freescale builds on the successful engagement we have had for more than a decade,” said Manoj Gandhi, senior vice president and general manager of the Synopsys Verification Group.

 www.synopsys.com

Tags: EDA, Freescale, IP, SoCs, Synopsys

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