Synopsys gives IC Compiler speed burst for place and route
Synopsys has introduced IC Compiler II place and route tool with new clock-building technology and advanced global-analytical closure techniques.
The multi-threaded place and route tool can handle designs with more than 500 million instances.
Block level functionality come from a new global analytical optimisation engine and there is a completely new clock generator and algorithmic capabilities in post route optimisation, which optimises results in area, timing and power.
IC Compiler II also incorporates technologies used in IC Compiler, such as the conjugate-gradient placer and the ZRoute router.
“IC Compiler II achieves its results with an average of 5X faster runtime and 2X reduction in memory over the first generation IC Compiler,” said Synopsys
The tool shipments start in mid-2014.