Synopsys has taken its FPGA-based asic prototyping hardware up to 144 million gates.
Dubbed the HAPS-70 Series, the units are based around Xilinx’ Virtex-7 FPGAs, and are available in models down to 12 million asic gates.
“The stacked silicon interconnect technology of the Virtex-7 2000T delivers two million logic cells of capacity and 12.5Gbit/s serial transceivers, making it ideal for ASIC prototypes which require both high capacity and high-speed I/O,” claimed Tim Erjavec, v-p of marketing at Xilinx.
Prototyping software aids partitioning and “automates the creation and debug of prototypes for a range of designs from individual IP blocks and processor sub-systems to complete SoCs”, said Synopsys.
Algorithms in the software are said to automate logic partitioning and live hardware queries to ease system bring-up compared to manual partitioning.
Some of Synopsys own interface intellectual property, including USB 3.0, PCI Express and HDMI, are already validated on HAPS systems.
“With pre-validated IP and a selection of daughter cards for common IP protocols, designers can start software development earlier in the product development cycle and reduce IP integration effort,” said Synopsys.
A ‘universal multi-resource bus’ (UMRBus) host connection option supports up to 400Mbyte/s bandwidth to link the hardware with the firm’s ‘Virtualizer’-based virtual prototypes to create a hybrid prototyping environment for early software development and hardware/software integration.
UMRBus also provides remote access, a generic C++/TCL programming interface and co-simulation with Synopsys’ functional verification tools along with hierarchical block level bring-up and debug.
“Increasing design size, software complexity and the earliest possible software development are key challenges for SoC prototypers,” said John Koeter, v-p of marketing at Synopsys.