Synopsys silicon IP for LPDDR4 memory

LPDDR4 architecture

LPDDR4 architecture

Synopsys has introduced intellectual property (IP) for LPDDR4  including a multiPHY, DDR memory controller and verification IP (VIP).

LPDDR4 is the latest generation of the high speed memory standard, designed to combine high data throughput with power efficient operation for smartphones and tablets.

The JEDEC standards body is expected to publish the specification this year.

LPDDR4 will effectively double the data bandwidth of its predecessor LPDDR3 to achieve 4.12Gbit/s.

LPDDR4 specifies a 1.1V VDD to lower power consumption. Pin-count has also been lowered to 6-pins by using CA encoding.

This is very much future technology. Most smartphones today use LPDDR2 (1Gbit/s) and LPDDR3 (2Gbit/s) mobile DRAM devices.

Apple is expected to uses LPDDR4 memory chips in its 2014 iPad, iPhone and Mac models.

Micron and Samsung are ramping up production of LPDDR4 mobile DRAM. Samsung has announced a 8Gbit LPDDR4 fabricated on 20nm process.

The LPDDR4 IP supports 3,200Mbit/s data rate performance needed for fast processors, high-resolution displays, HD video and graphics-intensive games in mobile SoC applications.

There are also power-saving features such as low-power modes (including power-down, self-refresh, and deep power-down), clock gating and power down of sections of the PHY that are not in use at a given moment.

A feature of the LPDDR4 IP is its support for a split PHY implementation to permit designers to distribute the IP around the SoC, optimising the interface for PoP assembly.

“Designers can take advantage of Synopsys’ DDR hardening and signal integrity services to harden the LPDDR4 multiPHY and to analyse the signal integrity of the entire system (silicon, package and PCB), easing IP integration and reducing potential risks in the use of advanced manufacturing technologies,” said the supplier.

There is backward compatibility with LPDDR3 and DDR3/4 SDRAMs.

The DesignWare Enhanced Universal DDR Memory Controller IP with support for LPDDR4 is available now. The DesignWare LPDDR4 multiPHY IP is scheduled to be available in Q3 2014 in a leading 16nm FinFET process technology.

Verification IP for LPDDR4 is scheduled for early availability in Q3 2014.

 

 

 

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