Tool tests JTAG coverage for PCB designers

Boundary scan chain integrity can be checked automatically on Altium’s Designer schematic capture and PCB layout software, using an extension from Cambridge-based XJTAG.

Xjtag Altium extension - Tool tests JTAG coverage for PCB designers

Called XJTAG DFT Assistant, and downloadable for free, it “provides engineers with an extension to check if boundary scan chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced,” said XJTAG CEO Simon Payne. “While the first prototype is being manufactured, XJTAG DFT Assistant allows you to export a preliminary XJTAG project from Altium Designer to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware, as soon as it’s available.”

The two parts of the assistant are: Chain Checker and Access Viewer.

  • Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected test access ports (TAPs), where a single connection error would stop an entire scan chain working. Incorrectly terminated TAPs are also identified.
  • Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan and, more importantly, which are not.

Boundary scan (IEEE 1149.x) gives serial access to all pins (or leads, pads or balls) on a chip package, allowing all connections into the chip to be exercised or probed, and all PCB traces and circuits connected to the chip to be exercised or probed.

A four or five-signal bus sequentially connects JTAG-enabled devices, looping from one chip to the next.

“Useful from prototype bring-up to production test, boundary scan allows a wide range of faults to be detected, such as short circuits, open circuits, stuck-at high/low faults and missing pull-up/down resistors,” said XJTAG – whose products automatically develop suites of boundary scan tests from design data.


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