TSMC validates Mentor tools for 3D stacking
TSMC’s 3D-IC design flow incorporates capabilities for metal routing and bump implementation, multi-chip physical verification and connectivity checking, chip interface and TSV parasitics extraction, thermal simulation, and comprehensive pre- and post-package testing.
Mentor’s Olympus-SoC place and route tool implements physical design for both silicon interposer- and TSV-based designs with support for cross-die bump mapping and checking; TSV, microbump, and backside metal routing; and copper pillar bump implementations.
The Pyxis IC Station custom layout product provides schematic-driven layout that supports a TSV design flow. It also enables both orthogonal and 45 degree redistribution layer (RDL) routing. Specific enhancements for the TSMC 3D-IC flow include improvements to the bump file import process.
The Mentor Graphics Calibre nmDRC and Calibre nmLVS tools provide inter-die design rule and layout vs. schematic checking, including IO alignment accuracy verification, and connectivity checking for double-sided bumps using either DEF or GDS input.
The Calibre xRC and Calibre xACT products extract parasitics for backside routing and single- or double-sided bumps defined in DEF or GDS formats.
They also handle TSV-to-TSV coupling extraction to drive static timing analysis and SPICE simulations, and generate TSV sub-circuit equivalents for multi-die parasitic models.
In the test area, the Mentor Tessent MemoryBIST product supports testing of stacked Wide IO DRAM die, while Tessent TestKompress provides die-to-stack level test pattern translations for both compressed and uncompressed test patterns.
Tessent IJTAG also supports 3D interconnect tests for dies wrapped with IEEE 1149.1 and 1500 style wrappers.
The FloTHERM software tool will also provide both static and transient thermal models for dies and 3D assemblies, and works with the Calibre RVE and Calibre DESIGNrev products to provide die and package level temperature visualisations.