Continuing our Industry Insider Interview Series, I caught up Joe Abler, Senior Member of Technical Staff at IBM Microelectronics. A seasoned veteran at IBM, Joe shares his thoughts on the on the semiconductor IP industry today and the challenges on the horizon.
Warren: Joe, it’s great to have you with us. Can you give me a little background on yourself and how you got into the IP business?
Joe: Early in my career, I was a chip designer in various product development groups in the fields of storage, networking, and display technologies. As such, I was an IP developer and user. That, along with my background in product design, enabled me to join IBM Microelectronics with the right skill set to help bridge the gap between customer IP and product requirements and process technology development.
WS: So, how would you rate the experience of working in IP versus other jobs you’ve held?
JA: It’s been great. In this field, I’ve been able to greatly leverage my product development background, as well as broaden my experience with other market segments and product sets through extensive relations with customers, partners, and suppliers.
WS: There has been tremendous consolidation of the IP market in recent years, with a number of the small and medium players getting gobbled up by the big guys. What does this tell us?
JA: I’m sure you’ll get feedback from IP vendors identifying the need for economy of scale, and I have no doubt that’s a big factor. From a semiconductor enablement perspective, there are also advantages to working with a few key suppliers. Each technology node is increasingly complex, and traditional brute force transistor scaling has long given way to the need for new materials, processes, lithography techniques, and so forth. This, in turn, increases the challenges in porting and validating IP to subsequent nodes, resulting in the need for semiconductor process and IP design to begin ever earlier in the development cycle, and for collaboration on what we term design/technology co-optimization. Such close collaboration is more manageable with a smaller number of key suppliers.
WS: The tech media of today, at least in the US, seems to have drastically shrunk. Famous editors are now working for product companies. How do you get your message out to customers in such an environment?
JA: I don’t know actual statistics in terms of size, but my perception is that it has evolved and transformed more so than shrunk. We are closer connected to our customers than ever through a variety of communication media and tools; our marketing is evolving with increased use of social media; and while we continue to use traditional media and event forums, we strive to do so in a more targeted manner.
WS: What’s the biggest change you’ve seen in the market since the meltdown of late 2008?
JA: The biggest change in our industry has been the shift to and growth of mobile computing and communications. While we can’t ever say what the trajectory would have been without the meltdown, it has been meteoric even in the face of it. The evolution of increasingly powerful CPU, GPU, and communications IP into highly integrated mobile SoC platforms; the competitive leverage of low power technologies and architectures; the rise of new operating systems; and the entrance of new industry titans along with the clash of the old—it all nets out to very exciting times we live in, and we’re really only on the cusp of this revolution.
WS: It wasn’t long ago that many IP companies were worried about licensing IP to China. Has that changed post-2008?
JA: I personally don’t believe it has changed, other than perhaps continuing to grow in importance. China represents huge opportunities that few will want to shy away from. Risk/reward of course needs to be appropriately evaluated, along with due diligence to business process.
WS: Let’s bring out our crystal ball for a moment. What do you predict will be the biggest, most disruptive change in semiconductors in the next three years?
JA: The industry is focused on innovations to continue reducing power and extending battery life. Our high-k metal gate technology provides continued scaling with lower leakage power and is now being extended to 20nm. The transition to 3D finFET transistor technology will enable continued reduction in supply voltage (which has leveled off in recent nodes) and, therefore, considerable reduction in active power. 3D techniques will also revolutionize packaging technology, providing the ability to stack and integrate multiple die within a single package. Such innovative packaging will enable increased bandwidth at lower power between processors and memory, allow for the integration of different process technologies optimized for different functions, and continue Moore’s law scaling at the subsystem level.
WS: It seems like there just aren’t any hot new startups anymore, while even industry titans are merging, as we saw with Texas Instruments’ recent acquisition of National Semiconductor. Are you apprehensive about such consolidations in the semiconductor industry?
JA: Not at all. With expenses dramatically rising, consolidation is inevitable. IBM recognized this trend a decade ago and formed strategic alliances within the semiconductor industry to collaborate on process development and share both costs and resources. Today, our Common Platform Alliance with GLOBALFOUNDRIES and Samsung remains a strong competitive model, as is evidenced by the fact that our collaboratively developed silicon lies under the covers of today’s most popular smart mobile devices. Such a collaborative model is really the only viable alternative to the few and shrinking number of players who go it alone.
WS: What would be your recommendations for new EE grads coming into the semiconductor world today?
JA: It’s a great time to be entering this industry. It’s a highly challenging field with enormous opportunity to innovate and make significant contributions. We have a chart based on the periodic table of elements, which we use to demonstrate the growing complexity in process technology. Prior to the 1990’s, there were half a dozen basic elements employed in silicon technology; following the 90’s, this grew to fourteen different elements, but since 2006, it has grown to over fifty. The point is: this is an exciting, stimulating, fast-paced field for R&D engineers. I might also add that it remains a strong and growing field within the US. Look at the activity in the Northeast, with the research and industry incubation driven by Albany Nanotech; the process development alliances led by IBM; the new 300mm fabs being built in the US by GLOBALFOUNDRIES, Samsung, and others; and of course the IP and EDA centres in Silicon Valley.
WS: Joe, as usual, you provide some great insights. Before we go: three words that you would use to describe the semiconductor industry today.
JA: Innovative, vibrant, and essential.
About Joe Abler, Senior Technical Staff Member, IBM
Joe Abler is a Senior Technical Staff Member in the IBM Systems and Technology Group at Research Triangle Park, North Carolina. Joe is a member of IBM’s Common Platform Strategy team, driving a technology and manufacturing collaboration of IBM, GLOBALFOUNDRIES, and Samsung Electronics. Joe’s responsibility is to develop and strengthen alliances with industry IP and EDA providers to build a comprehensive ecosystem enabling the Common Platform’s base technologies and delivering client solutions. He joined the IBM Microelectronics Division in 1999, bringing to the team over 20 years of experience in networking, storage, and consumer related technologies.
Warren Savage, President and CEO of IPextreme, is a well-known and published authority in the field of semiconductor intellectual property.
He has a long history of pushing the envelope of design methodology from his work in fault tolerant computing at Tandem Computers in the 1980’s and driving reliable design methodologies into commercial practice at Synopsys for its DesignWare IP product in the 1990s. Much of his thinking became embodied in the seminal book on IP reuse, the Reuse Methodology Manual.
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