Webinar: FPGA I/O optimisation for PCB design
A webinar to be presented by Zuken on April 1 at 2pm (GMT) will demonstrate an effective FPGA/PCB co-design environment utilising the latest devices offered by FPGA vendors, such as Xilinx, Altera, Lattice, and Microsemi.
“Making FPGA pin assignments without the consideration of component placement and routing can not only impact timing but make the PCB unroutable,” said Zuken.
The webinar will explore various points in the design flow where co-design of the FPGA or other programmable devices and board layout can take place; this includes library part creation, schematic entry, I/O optimisation and pin assignment management during board layout.
It will take place on 1 April 2014 at 2pm (GMT) and will last 50 minutes.
The presenter will be Nik Kontic, business development manager, Zuken USA. He has worked at Racal Redac and now Zuken for more than 25 years.
Zuken moves beyond EDA tools to data management