Xilinx launches its first SoC design tools
Xilinx is supporting its move into the processor-based system-on-chip (SoC) device business with a new design tool environment.
Called Vivado, it is a complete SoC design suite including IP and system-level design tools, different from what the FPGA supplier has offered before.
According to Xilinx, the tools are intended to “not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, analogue mixed signal and a significant percentage of semiconductor intellectual property (IP) cores.”
“Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers’ needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration,” said Xilinx senior vice president of platforms development, Victor Peng.
The existing ISE Design Suite will continue to be supported by Xilinx for customers targeting 7 series devices and prior generations. But for devices beyond 28nm, Vivado will be the only design tool.
The tool set has been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using the company’s stacked silicon 7 series devices.
The integrated design environment (IDE) has a new debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others.
It will support the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
The Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems.
Simulation is 3X faster and hardware co-simulation provides 100X more performance, said Xilinx.
There is a new hierarchical device editor and floor planner, a faster logic synthesis tool with support for SystemVerilog, and a more deterministic place and route engine.
The Vivado Design Suite version 2012.1 is available as part of an early access program. Customers should contact their local Xilinx representative.
Public access will commence with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 extensible processing platform (EPP) support later in the year.