Aldec offers 24 million gate Asic prototyping with Virtex-7
Aldec Europe has announced availability of its HES-7 FPGA-based Asic/SoC prototyping system.
HES-7 is based around a Xilinx Virtex-7 2000T 3D FPGA with a design capacity of up to 24 million Asic gates on a dual-device board.
There is an expansion capability for custom daughter boards or up to four HES-7 boards, delivering a total design capacity of up to 96 million ASIC gates.
“With most ASIC designs being between 10 and 20 million gates, to date it has been necessary to employ several low-density FPGAs on a single prototyping board; and implementing the SoC/ASIC design has been a painful and costly process because the design needs to be partitioned between the multiple devices,” said Zibi Zalewski, hardware division general manager at Aldec.
“Using a dual-chip HES-7 prototyping solution from Aldec, equipped with Xilinx’s industry-leading Virtex-7 2000T devices, reduces the design implementation effort and lowers the tool expense when supporting multi-million gate SoC designs,” said Zalewski.
The HES-7 also makes use of Xilinx’s latest Vivado design suite.