Cambridge firm streamlines DSP for low power wireless
Smaller, customisable cores can remove the DSP block to low power wireless product developments, writes Peter Goldsmith.
For battery powered wireless products traditional digital signal processors (DSPs) are often the largest, highest cost and most power-hungry components. This is a significant barrier to wireless product designers looking to improve performance, reduce cost and reduce size of their wireless Asics and FPGAs.
More often than not then the DSP is the key barrier to improving performance and cost reduction due to the need for optimised hardware.
At Cambridge Consultants we see many clients with similar requirements for their wireless Asics – fast predictable data processing and a rapid low-risk development programme. However, their applications can only be successful if the DSP function has similar cost and power consumption to an optimised hardware design; yet their system requirements, competitive landscape, or the fact that radio standards are not yet fully defined, mean that they need to retain software flexibility.
So what can wireless product designers do to get around these catch-22 design challenges of traditional DSPs?
Standard DSPs are designed to suit a wide range of applications and use cases and therefore contain overhead to support a range of features. These features take silicon area and hence cost, and they also consumer power even when idle.
One potential approach is moving to customisable DSP cores. For example Cambridge Consultants developed Sapphyre, a DSP core specifically for low power applications.
Compared to traditional DSPs, customisable DSP cores incorporate only those functions that are needed by the target application. Furthermore, the performance of these functions can be optimised to match the task that is to be performed.
This modular approach means that a complete core can be implemented in around 20 thousand gates and that means it is almost as efficient as a fully-optimised implementation of dedicated hardware.
No two implementations are the same, as custom modules are configured and added to the design as required. All modules within the core operate totally in parallel and are configured and controlled using very long instruction words (VLIW), typically up to 128 bits.
Usually, a DSP core like Sapphyre will sit alongside a standard embedded host processor as a specialised acceleration engine, and exchange data with this processor via two blocks of shared dual-port memory.
One block is for DSP code (loaded by the host processor and executed by the core) and the other is for data to be processed.
The use of parallelism means that DSP cores approach the efficiency of a design based purely on hardware. Yet, unlike a fixed hardware design, the precise function is not frozen at Asic tape-out; software modifications can continue to be made as issues are found during system integration and test.
Short-burst data modem for Iridium
In 2006 Cambridge Consultants designed the successful 9601 short-burst data modem, opening up a completely new market area for Iridium Communications, this is one of machine-to-machine (M2M), asset tracking, location and automation.
For the first time, end users could deploy systems to inaccessible and remote locations and still monitor and control these systems from central control rooms.
The 9601 was a popular product with users, but Iridium could see that market penetration could be increased dramatically if the modem could be compressed into a smaller package and produced and sold more cheaply.
In the 9601 modem, the DSP chip was easily the most expensive single component and was a key barrier to cost-reduction. It was clear that it would be relatively straightforward to design a custom chip incorporating the host processor, its RAM and the logic from an existing gate-array, but this would not be worthwhile exercise unless the DSP could also be eliminated from the parts-list.
A traditional DSP would not be well suited to be a block in a low-cost custom chip, even if a licence was available for the logic design, as it would have far too high a gate count. The breakthrough in the Iridium project came from the realisation that the existing DSP software design could be adjusted to run on two Sapphyre cores.
The DSP core was incorporated into a baseband Asic, together with a matching RF/analogue IC, to significantly reduce the size and complexity of the radio IF block.
These new components were used to produce the 9602 modem, launched in 2010.
The 9602 is 69% smaller and 74% lighter than the 9601. The space taken by the baseband circuitry has been reduced even more dramatically: circuitry which previously occupied a PCB area of size 50 x 45mm has been compressed into a single 10 x 10mm package – a 95% reduction.
There have been cost savings which mean that the 9602 can be incorporated into new, more cost-sensitive applications. The small silicon area taken by the Sapphyre logic costs only a few cents, meaning that the DSP function has changed from being the most expensive part of the design to being the cheapest.
In this way we can see how customised DSP cores can reverse the traditional design challenge of DSP in low-power wireless applications.
They present an opportunity for designers to take DSP-based products into new markets, add functionality, increase performance and enable new tasks that would almost certainly have not been possible with hardware-based processing design.
So customised DSP cores are not just DSPs without the cost and size drawbacks, they are in fact a complete performance upgrade, even compared to custom hardware – opening a whole new spectrum of possibilities for wireless product designers.
Peter Goldsmith is senior consultant in the wireless division at Cambridge ConsultantsTags: Cambridge, CCL, design, dsp