FPGAs are ready to take on Asics, says Xilinx CTO

FPGAs now have the performance, cost structure and power efficiency to go after mainstream Asics designs like never before, says Ivo Bolsens, chief technology officer at Xilinx.

He was speaking as Xilinx announced it was shipping commercial devices of its highest capacity FPGA, the Virtex-7 2000T which has 6.8 billion transistors.

“This chip has the equivalent of 20 million Asic gates and we will be going after established Asic markets with it for the first time,” Bolsens told Electronics Weekly.

“We have the performance level to do this now,” said Bolsens. “Real customers are already designing with it.”

This is a massive FPGA in every sense of the word and it needs to be if Xilinx is to make any impact on ‘hard-core’ Asic designs it is going after in the telecoms and video processing markets.

A single chip of this size would be hugely problematic to manufacture, so Xilinx has built it from four smaller FPGA die which are connected using through-silicon via (TSV) interconnect layer.   

“There are more than 10,000 interconnects between the FPGA die, this is what TSV technology gives us, it makes this level of performance and complexity possible for the first time,” said Bolsens. 

“TSV is the most revolutionary technology we have introduced during my years at Xilinx,” said Bolsens. “We absolutely need this technology.”

The performance of the Virtex-7 2000T is twice that of any chip Xilinx has produced. Bolsens demonstrated it with the example of a telecoms customer which had replaced a development system consisting of 64 Virtex-6 FPGAs with 16 Virtex-7 2000Ts.

The big target for these devices are the mainstream Asic market, for a long time beyond the reach of FPGAs in terms of performance, power and cost.

Bolsens believes the performance and power consumption of this 28nm chip will take FPGAs into mainstream Asic designs for the first time. 

There have been big FPGAs before what’s new is the use of TSV to build an even bigger chip from four smaller ones. On a process that Bolsens believes will be cost competitive with Asics.

“The key factor is our aggressive use of stacking system-in-package technologies,” said Bolsens.

“TSV breaks the exponential dependency of yield in wafer production,” said Bolsens.

Bolsens said the FPGA had been shipping since September.

www.xilinx.com

Tags: Asics, design, FPGAs, Xilinx

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