Mips adds security and SIMD
Mips Technologies had added virtualisation and 128bit SIMD instructions to its 32 and 64bit architectures, taking them to Release 5.
Virtualisation hardware is for security – allowing multiple operating systems to run on a single core with no possibility of data interaction. A banking application, for example, can safely run at the same time as web browsing.
Single instruction multiple data (SIMD) functions are used when the same instruction needs to be executed on several independent data words. They are used to speed video, audio, graphics processing.
“SIMD is popular for multi-media,” MIPS product director Mark Throndson told Electronics Weekly. “We have a more modest 32bit implementation of SIMD in our DSP extension. The new one is stronger, it has 128bit words initially and architecture is extendable to be wider in future while maintaining software compatibility.”
The new SIMD block is not back-compatible with the existing one in the firm’s DSP extension, but it will be forward-compatible with later wider versions, said Throndson.
It is designed for performance with 32 x 128-bit vector registers per thread, said the firm and can operate with 8, 16 and 32bit integer and fixed-point data types as well as 32 and 64bit floating-point.
Mips supplies its intellectual property at two levels: as an instruction set (known at Mips as the ‘base architecture’) to its architecture licensees, and as RTL to licensees of its cores.
“These new technologies are in the MIPS base architecture, available to our architecture licensees, but are not yet implemented in MIPS processor cores. The technologies will be added to MIPS cores in the future,” said Mips spokeswoman Jen Bernier-Santarini.
“Key features of the MIPS architecture R5 specification are available for licensing now. Several MIPS licensees already have products in development. These features are expected to be added to MIPS processors in the coming year,” said the firm.
Previously, in Release 3, the new instructions would be added to the architecture as optional components that the firm called ‘application-specific extensions’. The existing DSP block is an example of this, as is the firm’s multi-threading extension.
In a change of strategy, the DSP, multi-threading, virtualisation and SIMD blocks will now be known as ‘modules’ and will always be supplied.
“The primary difference is that four elements are in base architecture, there is nothing functionally different at all,” explained Throndson.
The form has jumped straight from Release 3 to Release 5. “There was no Release 4 for marketing reasons,” said Throndson.
In many ways, these changes do not constitute a new architecture, but the addition of major functional blocks the existing architecture.
The virtualisation block
The last change to the underlying architecture was revealed with the introduction of Aptiv branded processor cores in May this year.
Aptiv signalled ‘enhanced virtual addressing’ which was done before Release 5, said Throndson. “It was an improvement to previous way the architecture worked.”
Enhanced virtual addressing tripled the amount of memory that could be addressed by the 32bit address bus.
“Mips, ARM, x86 and PowerPC have all been around for a long time. When they were defined, software had different workloads than software has today. Most architectures are limited to approximately 1Gbyte before page swapping,” said Throndson. “Enhanced virtual addressing makes better use of 32bit resources: it makes the virtual address map programmable so the operating system can make better use of the 32bit address space. 32bit should go to 4Gbyte. Our enhanced virtual addressing allows over 3Gbyte.”