Xilinx acquires ESL firm to make FPGAs easier to use

Xilinx plans to add System C high level design to its 6- and 7-series FPGA families with the acquisition of design tool firm AutoESL Design Technologies.
 
According to Tom Feist, a senior marketing director at Xilinx, the use of level-higher design synthesis in System C, as well as C and C++, will “address the ease of use issues” which have sometimes been a barrier to using FPGAs.

No longer will designers be required to have knowledge of design in RTL for their FPGA developments. 

“It will broaden the design community for FPGAs with designers more accustomed to designing at a higher level of abstraction in C, C++ and System C,” said Feist.

AutoESL’s high level synthesis tool is called AutoPilot has been used by semiconductor and systems companies in designs for video, wireless, and high performance computing applications.

Xilinx will continue to support these following the sale and then will quickly introduce its own branded standalone tool for its 6- and 7-series FPGAs.

Following this the company will work on integrating the high level tools more tightly into its existing design flow. This will involve support for the AXI-4 interface standard Xilinx is adopting for future devices.

The AutoPilot high level synthesis tool will generate register transfer-level (RTL) code foe specific Xilinx FPGAs.

Feist said that designers will also see faster verification time due to the advantage of working at a higher level of abstraction in C, C++ or SystemC.

Xilinx did not disclose terms of the acquisition. The majority of AutoESL employees currently located at the company’s headquarters in Cupertino, California and Beijing, China, will become Xilinx employees.

Tags: design, ESL, FPGAs, system C, Xilinx

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