Xilinx, MathWorks and National Instruments work on high-level FPGA design

zynqXilinx  is working with MathWorks and National Instruments to offer IP-based design environments for its Zynq system-on-chip FPGA devices.

The design tools offer graphical and text-based programming languages such as C, C++, SystemC, and will soon support OpenCL (Open Computing Language).

Xilinx is developing a system-level, Eclipse-based heterogeneous parallel programming environment that supports software-based programming, system verification, debug and automated implementation for C/C++ and OpenCL.s an alternative to traditional RTL-based FPGA design flows, IP integration and C-based design is used to accelerate development of complex FPGAs and SoCs.

“By expanding the number and type of abstractions designers can choose from, we are not only improving productivity for existing hardware customers, but are empowering the vast number of systems and software engineers to directly leverage All Programmable FPGAs, SoCs, and 3D ICs,” said Tom Feist, sr. director, Design Methodology Marketing at Xilinx.

Xilinx says IP Integrator (IPI) in its Vivado design tool is tuned for MathWorks Simulink designs built with Xilinx’s System Generator, and C/C++ and System C synthesised IP with Vivado High-Level Synthesis (HLS).

“Systems engineers prefer abstractions such as C/C++/SystemC, OpenCL, MathWorks MATLAB and Simulink, and National Instruments LabVIEW to model the hardware and software behavior,” said Xilinx, and now it is possibe “to take these algorithms directly to implementation without worrying about implementation details”.

MathWorks has released a new guided workflow for Zynq-7000 All Programmable SoC devices with their R2013b release.

The guided workflow enables software developers and hardware design engineers to create and model their algorithms in MATLAB and Simulink, partition their designs between software and hardware, and automatically target, integrate, debug and test those models on Xilinx targeted design platforms.

Embedded system designers can use LabVIEW and National Instruments reconfigurable I/O (RIO) hardware to abstract the complexity of traditional RTL design and avoid the time consuming tasks of building an operating system, drivers, and middleware for deployment targets.

 

 

 

Tags: SystemC, Xilinx

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