How to use solar power to charge batteries efficiently

Jay Celani, design engineer with Linear Technology, describes the design of a solar battery charger which maintains its efficiency in low light conditions

An important characteristic of any solar panel is that it achieves peak power output at a relatively constant operating voltage (VMP) regardless of illumination level.

The LT3652 2A battery charger is designed to exploit this characteristic to maintain a solar panel at peak operating efficiency by implementing input voltage regulation (patent pending).

A solar panel produces maximum power at a particular output voltage, VMP, which is relatively independent of illumination level.

A solar panel produces maximum power at a particular output voltage, VMP, which is relatively independent of illumination level.

When available solar power is inadequate to meet the power requirements of the battery charger, input voltage regulation reduces the battery charge current. This reduces the load on the solar panel to maintain the panel voltage at VMP, maximising the panel output power. This method of achieving peak panel efficiency is called maximum power point control (MPPC).

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While MPPC optimises solar panel efficiency during periods of low illumination, the power conversion efficiency of the battery charger suffers when power levels are low, degrading the overall power transfer efficiency from the panel to the battery. This article shows how to improve battery charger efficiency by applying a simple PWM charging technique that forces the battery charger to release energy in bursts when power levels are low.

Using the Current Monitor Status Pin to Indicate Low Power Conditions

The /CHRG current monitor status pin on the LT3652 indicates the state of battery charge current, and is used here to control the PWM function. The pin is pulled low when the charger output current is greater than C/10, or 1/10 of the programmed maximum current, and high impedance when the output current is below C/10.

During periods of low illumination, the input regulation loop can reduce the output current of the charger to below C/10, causing the /CHRG pin to become high impedance. This status pin change-of-state is used to disable the IC by triggering an input undervoltage lockout (UVLO) with the falling threshold at a solar panel voltage that is higher than the input regulation voltage (VIN(REG)). The solar panel voltage climbs through the UVLO hysteresis range in response to the charger being disabled until the UVLO rising threshold is achieved, when the charger is re-enabled at full power.

The charger then provides charge current until input voltage regulation again disables the charger. This cycle repeats, generating a charger output that is a series of high current bursts, which maximises the efficiency of the charger as well as the efficiency of the entire solar charger system at any illumination level.

Figure 2 shows a solar panel to 3-cell Li-Ion charger with low power PWM functionality. This charger employs a 17V input regulation voltage (a common VMP for “12V system” panels), programmed using the resistor divider R4 and R5 at the VIN_REG pin.

Keeping the operating voltage of a typical 12V system solar panel near its 17V rated VMP voltage yields panel efficiencies close to 100%. The low power PWM function is implemented using M1, R6, R7 and R8.

The charger IC’s /CHRG pin is pulled low while required charge current exceeds 1/10 of the 2A programmed maximum charge current, or 200mA. When charge current is reduced by the input regulation loop below the 200mA level, the /CHRG pin becomes high impedance, which allows the gate of M1 to be pulled up to VBAT, enabling the FET, M1.

17V VMP solar panel to 3-cell Li-ion (12.6V) 2A charger

17V VMP solar panel to 3-cell Li-ion (12.6V) 2A charger

This FET pulls R7 to ground, engaging an input voltage UVLO function using the SHDN pin and the resistor divider made from R6 and R7. The UVLO function is programmed with that divider to have a falling threshold of 18V and a rising threshold of 20V.

The falling threshold is the critical design value, and must be programmed to a voltage that is higher than the input regulation voltage, and is 10% lower than the rising threshold, as is dictated by the shutdown threshold hysteresis.

During low illumination conditions, when available panel power is insufficient for the device to provide required charge current, the IC’s input voltage regulation reduces the output charge current until the charger input power is equivalent to the available power provided by the panel. With input regulation active, the panel voltage at VIN is held at the programmed 17V peak power voltage, maximising the power produced from the panel. If the panel illumination becomes low enough that the available panel power corresponds to charge current less than 200mA, the /CHRG pin becomes high impedance and the UVLO function is enabled via M1, R6 and R7.

Since VIN is at 17V, which is lower than the UVLO falling threshold, the IC shuts down, disabling all of the battery charging functions. With the battery charger disabled, virtually all of the panel output current charges the input capacitor (C1), increasing the voltage at VIN until the 20V UVLO rising threshold is achieved, re-enabling the device.

The battery charger is re-enabled with VIN well above the 17V input regulation threshold, so full charge current flows into the battery. The /CHRG status pin is pulled low in response to the high battery charge current level, which disables the UVLO function.

As long as the power required by the battery charger remains less than that available from the solar panel, the panel voltage will collapse until VIN is reduced to 17V, when the battery charge current is reduced by input regulation to maintain that voltage. When the charge current is again reduced to 200mA, the /CHRG pin becomes high impedance, the UVLO circuit is reengaged, and the disable/enable cycle repeats, resulting in a string of charge current ‘bursts’ that average to the battery charge current corresponding to the available power from the solar panel.

LT Scope Photo Labels CS5 7.0Figure 3 shows the PWM operation of the circuit in Figure 2. While the LT3652 is disabled, the voltage on VIN ramps from the input regulation threshold of 17V to the shutdown threshold of 20V. The voltage on the /CHRG pin is low while the charger is enabled and high while the charger is disabled. While the charger is disabled, the panel energy is stored in the input capacitor, so the output power from the panel remains continuous. The efficiency of the solar panel corresponds to the average voltage on the panel during PWM operation, which is about 18.5V.

Lead-acid battery charger design

Figure 4 shows a 6-cell lead-acid battery charger with low current PWM functionality. The battery charger is designed for a solar panel that has similar characteristics to that used for the charger in Figure 2.

This lead-acid charger performs a 3-stage lead-acid charging profile, employing 2A bulk mode charging, absorption mode charging to 14.4V, and float charge maintenance at 13.5V.

The battery charger provides up to 2A while charging with CC/CV characteristics up to the absorption mode regulation voltage of 14.4V, provided there is ample input power available from the solar panel. As the battery nears the 14.4V regulation voltage, charge current is reduced, completing absorption mode charging when the charge current falls to 200mA, or 1/10 the maximum charge current (C/10).

LT Journal Guides—Single-PageWhen absorption mode charging is completed, the /CHRG pin becomes high impedance in response to achieving the C/10 charge current threshold, and float mode maintenance charging begins. The regulation voltage is reduced from 14.4V to 13.5V in float mode, achieved by effectively removing R9 from the VFB summing node—accomplished by a diode-OR circuit (D4 and D5) when /CHRG is pulled high by R8, via the reverse-biased D4.

Float mode charging regulation is also implemented if the charger experiences inadequate input power due to low solar panel illumination levels. If charge current is reduced to less than 200mA via input regulation and PWM operation begins, the /CHRG pin voltage becomes a pulsed waveform. D5 and C5 implement a peak-detect filter that maintains a continuous reverse-bias on D4, keeping the charger in float mode (VCHARGE = 13.5V) during PWM operation. Figure 7 shows that the addition of the PWM circuitry increases efficiency at battery charge currents below 200mA.

During PWM operation, the input voltage ramps from the input regulation threshold of 17V to the shutdown threshold of 20V during the period the IC is disabled, as previously described for the battery charger in Figure 2.

The output power from the solar panel corresponds to the average voltage of the panel, or about 18.5V. To maximise both solar panel output efficiency and battery charger efficiency in applications with extended low light operation, the VIN(REG) and UVLO voltages should be reduced during the burst period. A method to do so is described below.

Lead-acid battery charger with low current VMP tracking

The lead-acid battery charger shown in Figure 5 is similar to the battery charger in Figure 4, but also lowers the input regulation voltage (VIN(REG)) while the charge current is below 200mA. This improves panel efficiency by tracking the panel’s characteristic reduction in VMP at low currents.

17V VMP panel to 6-cell 2A lead-acid charger with low current VMP tracking

17V VMP panel to 6-cell 2A lead-acid charger with low current VMP tracking

Low current VMP tracking is implemented by adding R10 to the input regulation divider of R4 and R5. R10 is connected to the input regulation summing node through a diode-OR circuit (D6 and D7). When the /CHRG pin voltage is high, R10 is effectively removed from the summing node via the reverse-biased D7, lowering VIN(REG) from 17V to 15V.

If the charger experiences inadequate input power due to low illumination levels, charge current is reduced via the input regulation loop to maintain the VMP solar panel voltage of 17V.

If charge current is reduced to less than 200mA, the charger begins PWM operation and the regulation threshold is reduced for float charging, as in the previous lead-acid battery charger circuit. Additionally, this charger reduces VIN(REG) to 15V, tracking the reduction of the solar panel VMP at low currents.

D6 and C6 implement a peak-detect filter, similar to the previously described D5 and C5. This filter maintains a continuous reverse-bias on D7, keeping the charger input regulation voltage at the 15V low illumination level during PWM operation. The PWM control components (M1 and R6-R8) implement UVLO thresholds of 16V (falling) and 17.5V (rising).

During PWM operation, the panel voltage at VIN ramps from the 15V input regulation voltage to the 17.5V UVLO rising threshold, yielding an average panel voltage of about 16.25V. This charger maximizes both charger conversion efficiency and solar panel output power efficiency by reducing the operational panel voltage while implementing PWM operation during periods of low illumination.

 

 

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