Free boundary scan test workshop in Cambridge
Targeted at design, test and production engineers, the sessions will provide an introduction to JTAG boundary scan and the IEEE 1149.x standard.
“In an age where chip and board geometries continue to shrink, working at higher speeds and greater densities, traditional test technology falls short in terms of access and coverage,” said the company.
“Boundary scan provides a cost-effective, non-intrusive test solution that pushes beyond these limitations.”
Sessions will show how boundary scan can be used from start to finish, both to improve designs and reduce respins as well as to enhance test coverage, fault diagnosis and production yields on complex BGA-populated circuits.
Workshops will also cover how to test non-JTAG devices using boundary scan.
‘The introduction to boundary scan is an ideal opportunity for engineers involved in design and manufacture to discover how using XJTAG can speed up the process of debugging and testing their boards throughout the product lifecycle,’ says Simon Payne, CEO XJTAG.
The workshop will be held on Tuesday 21st January and is open to electronics engineers and academics alike.