Leakage and verification costs both continue to rise, says Cadence

The greatest barrier to the adoption of low-power techniques to chip design is the reluctance of designers to take a risk when they are up against time constraints, according to Bill Heiser, group director for digital implementation and low power at Cadence.

“The biggest obstacle to adopting a new technique is risk. Design teams have to get to working silicon, that is their priority”, said Heiser.

Cadence has clocked over 100 tape-outs at over 40 customers for its low-power design tool which implements power reduction techniques such as clock gating, multi supply voltage, multi Vt optimisation, power shut off, dynamitic and adaptive voltage frequency scaling.

However, the bad news is that leakage continues to get worse as processes scale down to smaller geometries. Asked if leakage was still getting worse with ever new process node, Cadence’s Pankaj Mayor replied: “Leakage still gets worse.”

The other bad news for the IC industry is that verification costs continue to rise as a percentage of the cost of designing a chip.

Asked if verification cost would continue to rise as a proportion of total cost, Dave Tokic, director of verification IP at Cadence, replied: “I expect it will.”

Tokic added that customers are telling him that verification cost amounts to 70 per cent of total design cost.

Cadence has an OVM (Open Verification Methodology) verification tool which, claims Tokic, “Saves months off verification projects.” That sounds good, but the rapidly rising complexity of ICs still dictates that verification costs will keep rising more than overall design cost.

Cadence has appointed an ‘interim team’ to take over from the four top executives including the CEO, who resigned recently.

The company is still not revealing the reason for the departure of the four, but it may not be unrelated to the fact that the company has delayed its third quarter earnings announcement, and has called in the lawyers and auditors to determine whether first quarter revenues were incorrectly stated.

It is suggested that $24m in revenues were accounted for in Q1 when they should have been spread over the duration of the contracts.

Meanwhile the company is saving $23m, the combined annual compensation of the four execs which, one wag pointed out, is equivalent to ten cents on the Cadence share price.

David Manners, Silicon Valley

See also: Mannerisms, the blog of David Manners. Updated twice daily, it’s the distinctive, entertaining, authoritative and never dull commentary on the semiconductor industry, from someone who knows. Sign up for the Mannerisms eNewsletter.

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Tags: Cadence, chip design, verification

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