Unwanted noise? Deal with it

Unwanted noise is introduced in all electronic circuits and providing sufficient noise margin for Vcc and GND specifications is paramount, writes Howard Venning

Unwanted noise is introduced in all electronic circuits, and all switching devices induce GND and Vcc noise.  Additional sources add their part of noise onto clock lines, data busses, reference lines and more. Finally, power supply ripple and noise caused by load changes effects as well.

Providing sufficient noise margin for Vcc and GND specifications is paramount for flawless functionality of ICs.

Circuit designers are well aware of noise and jitter effects on clock and data lines; effects that may threaten data integrity and proper functionality of their systems. Once the causes of such unwanted noise are pinpointed their effects can be minimised for optimal operation with minimal BER problems.

However, a “new” kind of noise has started to interfere with the functionality of electronic systems – Vcc and Ground noise, with major culprits called GND Bounce and Vcc Droop Jitter. 

While Vcc specifications of ICs define the operational range, high frequency noise can disturb their functionality, even when operated within specified Vcc limits. Such disturbances can enter the circuits through residual capacities on the chip.

The usual recommendation of placing a blocking capacitor adjacent to the Vcc pin may no longer be sufficient.

Why does Vcc noise influence system functionality?

Switching behaviour of digital circuits depends on defined threshold levels that determine if a signal is considered a logical “1” or “0”.  Switching time can shift with varying Vcc levels, even if data input signal levels are constant. While chip designers try to minimise jitter effects caused by Vcc variations, their effects cannot completely be eliminated.

Digital threshold decisions are to some degree always depending on the Vcc power level, even if Vcc varies just within its allowed limits. While general chip functionality is provided within that Vcc range and the IC works as specified, Vcc variations cause slight changes in the switching responses. This means Vcc and GND noise cause output signal jitter.

Analogue circuits respond to noise present in Vcc or GND lines. The effects can even multiply if the circuit amplifies signals. Vcc noise will usually influence timing and purity of output signals. Vcc noise generated directly on the chip can even create unwanted noise loops, which again can significantly influence functionality of electronic systems.  

Causes of Vcc Noise

Close proximity of high-speed data traces in PCB layouts can create distortions caused by Inter Symbol Interference (ISI), Inter Carrier Interference (ICI) or other unwanted distortion.

Power supplies are well known for generating deterministic jitter (DJ), effecting both, power traces and data lines. The cause can be linked to power supply switching frequencies and their harmonics.

Every electronic component, passive or active, generates a distinct amount of noise energy, caused by thermal random movement of charge carriers and amplifying (active) devices multiply this and any other noise. These problems are a well-known and particular care should be taken on data and clock lines. The increased switching speed can cause noise problems at Vcc or Ground lines.

Both GND planes and Vcc lines usually have extremely low impedance, which has so far rendered noise negligible. In addition, the use of block capacitors in close proximity to the chips’ power and GND pins has helped reduced any jitter and bounce effects.

Unfortunately though, these measures cannot eliminate the effects completely, particularly not if the noise is generated within the circuit. 

In a very fast switching environment, inherent line inductances and capacitances can cause frequency dependent jitter on data lines which in turn generate noises on GND and Vcc lines. This effect is called Vcc-Droop Jitter and Ground Bounce.

The faster circuits switch, the more noise they generate. The effects are multiplied with simultaneously switching (parallel) I/O ports.

itemid-55036-getasset.jpg

Figure depicts the active parts switching, from “0” to “1” and figure 5 shows an output change from “1” to “0”.

Thresholds determining the logical state are directly dependent on the level potential difference between GND and Vcc. Noise from either plane can cause early or delayed output response. In extreme cases it will result in spikes at the output ports and cause unrecognized information on the data bus. Clean and stable Vcc and Ground levels are mandatory to prevent such disturbances that can significantly influence system functionality.

Self-induced Vcc and GND Noise

Ground Bounce occurs when integrated circuits switch their high speed output ports from “1” to “0”; Vcc Droop happens when they switch from “0” to “1”. With Ground Bounce, the device ground rises relative to the power supply ground.

Conversely, with Vcc Droop Jitter, device Vcc drops relative to the power supply ground and the power supply Vcc. The amount of bounce or droop depends on the rise or fall times of the switching output ports. It multiplies with the number of simultaneously switched output pins.

Ground Bounce

Figure 4 illustrates the path between power supply; board; device output and output trace. The path can be described as four inductances (L1GND to L4GND) that are connected in line supplying the die GND.

Voltage response of inductances is a function of current and change time with the resulting voltage being described as in the following equation: V = L(sum) × (dI / dt) 

- V is the voltage difference between the die Vcc and power supply Vcc,
- L(sum) is the sum of all path inductances (L1, L2 L3 and L4)
- dI the time increment in which the current change happens.

An inherent capacity withi n all data output traces plays also an important role. This capacitance is charged as the output drives a logical “1”. When the output switches back to “0”, the charge has to be released through the Lo-transistor, resulting in a current initiated from the data trace capacitance to the die pin ground and it continues to the power supply ground.

Because of relatively small data path capacities, these currents are quite small but because of the in-line inductances, it can cause significant spikes with fast switching times. Block capacitors adjacent to the chip pins cannot eliminate all of the energy from these spikes.

Conversely, VCC droop Jitter occurs when ICs switch outputs from “0” to “1” at high speed. The Vcc drops relative to the Power Supply Vcc.

Howard Venning is managing director of Aspen Electronics

Tags: design, power, test

Related Tech News

Share your knowledge - Leave a comment