European design conference looks at the world after Moore’s Law
Ryder will consider the alternatives to shrinking feature sizes in his keynote presentation at Mentor Graphics’ European user conference takes place at the Park Hilton in Munich on October 17.
“For decades, we’ve known it was coming and now it’s here,” says Ryder.
“Moore’s Law, which is really just a special case of the “learning curve, can no longer drive the 30% per year reduction in cost per transistor, beginning with the 20/16/14nm generation,” says Ryder, who will give a keynote presentation at the conferenece titled: “The Big Squeeze”.
“Either we find innovations beyond just shrinking feature sizes and increasing wafer diameter or we slow our progress down the learning curve, introducing innovative new electronic capabilities at a slower rate than in the past,” says Ryder.
Other presentations will cover topics such as functional verification and emulation, analogue mixed-signal and physical verification and design for test, PCB design and analysis and IC design and test.
A keynote presentation from Arunjai Mittal, member of the management board of Infineon Technologies will discuss how energy efficiency can be achieved with semiconductor design.
One of the presentations, from Sondrel verification consultant Hélène Wood, will discuss Questa Power Aware simulations using UPF files.
Simulating with UPF files is used for checking power management implementation in a design. The presentation is targeted towards those new to UPF, will explain what it is and include a discussion on the UPF Verification flow.
The advantages and disadvantages of UPF will be covered, as will the importance of introducing UPF early in the design flow to help find any power related issues.
Gianvito Lorusso, engineering manager, is speaking on the use of Olympus-SoC place and route software in a large 28nm design with over 70 million nodes.