Cadence addresses extraction issues of finfets and double-patterning
Cadence Design Systems has enhanced the performance of its parastics extraction tool to address the challenges of chip design using double patterning process technology and finfets.
The tool is used in digital and analogue chip design to calculate resistance and capacitance parasitics of on-chip interconnect.
And the reason for the enhanced performance?
KT. Moore, senior group director, digital and signoff group points out: “Advanced process nodes need faster extraction and greater scaling predicatability. At sub-20nm nodes, double-patterning dramatically increases complexity of the rules. Finfets need more exact extraction accuracy.”
Cadence’s latest RC extraction tool called Quantus QRC Extraction makes use of parallel computing techniques to speed up the design process and design signoff.
According to Cadence, the tool has been certified for finfet processes by TSMC.
“It is a sign-off quality extraction tool,” said Moore.
The speed and accuracy of the tool comes from a random-walk field solver called Quantus FS and an automated incremental extraction capability reduces design closure when used with Cadence’s Encounter Digital Implementation System and Tempus Timing Signoff Solution.