MIPS unveils microcontroller core
MIPS has revealed cores to compete with ARM‘s Coretx-Mx series.
Called Warrior M, and available in microcontroller and microprocessor flavours, they are based on existing microAptive cores, with three added features: hardware virtualisation, a floating point unit, and anti-tamper (see below).
Performance is 1.57Dmips/MHz and 3.44CoreMark/MHz, MIPS business development manager Ian Anderton told Electronics Weekly, emphasising that this is running compact code, not expanded code using ‘in-lining’ to boost benchmark performance.
Virtualisation allows a core to run multiple operating systems, time-sliced onto the core without them having any knowledge of each other. In this case, it is full hardware virtualisation, so operating systems run with “no software modification required”, said Anderton. Any mixture of up to seven ‘guests’ (operating systems, apps, kernels, schedulers or supervisors) can run.
“If one crashes, the others do not,” said Anderton, allowing a Linux user interface to run alongside control software without endangering the control function. Virtualisation also prevents the hacking of one application through another.
“Security and reliability are must-haves in embedded systems. It’s especially critical for connected products,” said MIPS.
Warrior M comes in two flavours: M5100 and M5150.
M5100 is nominally the microcontroller core, with “lightweight virtualisation”, said MIPS, using a root/guest fixed mapping translation (FMT). It has a root protection unit, and instruction and data SRAM controllers.
M5150 has both instruction and data L1 caches, and is aimed at what MIPS calls ‘microprocessor’ applications. Its virtualisation is more comprehensive than in the 5000, coming from a root/guest translation look-aside buffer (TLB) memory management unit (MMU).
The TLB, a type of cache, converts virtual to physical addresses. “For Linux, everything is virtual,” said Anderton.
Hypervisor software for virtualisation comes in two forms from MIPS:
KVM (kernel virtual machine) is a Type II hypervisor implemented at a kernel module within Linux and uses some existing Linux kernel features.
For more security, Fiasco-OC is a Type 1 level four micro-kernel hypervisor whose virtual machine runs in root-user context. “User application services and libraries are provided by the L4 runtime environment,” said MIPS.
Neither hypervisor is fully-released yet. Both are available for evaluation. According to MIPS, other hypervisors are being developed by partner companies.
Anti-tamper features include user-defined scrambling of RAM and scratch-pad RAM data and addresses.
Random pipeline stalls can be injected to hamper timing and power analysis, and two pseudo-random number generators are provided for user software and core logic.
“It is secured against external memory, address and power probing,” said Anderton. If they de-cap the SoC, we still provide some level of logical anti-tampering.”
The floating point unit option offers single (32-bit input) and double (64-bit input) precision.
Isn’t 32-bit enough for anyone?
“Double precision has application in Android and web browsers,” said Anderton. “There has been a lot of lazy coding practice where software is written with the idea that there is a set of resources that get used whether the application truly requires 64 bits or not. This is difficult to re-write, so it has become easier to support the basic hardware requirement.”
MIPS is claiming 576MHz operation on a 28HPM semiconductor process, with typically <20mW dynamic power and <0.3mm2 chip area.
“You can configure-out parts [see options on diagram] to reduce size and speed,” said Anderton. “If you target 300MHz rather than 500MHz, it is easier to implement, so the number of gates goes down even with the same functional implementation.”