Altera to use TSMC’s low power 28nm process
Altera is going to use TSMC’s low power (LP) 28nm process as well as its high performance (HP) 28nm process.
The LP process will be used for low-cost and mid-range product.
“In today’s highly fragmented markets, it is imperative we provide customers a choice”, says Vince Hu, vice president of product and corporate marketing at Altera.
Altera sees the LP process as suitable for cost-sensitive applications in the automotive, industrial and wireless markets where minimising power consumption and cost is paramount.
Using both LP and HP process technology enables Altera to address more ASIC and ASSP opportunities across all market areas.
Altera will begin taping out its 28-nm Stratix V FPGA by the end of 2010 and will have engineering samples available to customers starting in Q1 2011. Customers can start their Stratix V FPGA designs by using Altera’s Quartus II software. Additional 28-nm FPGA families will be announced in 2011