Intel’s finfet shape a liability, says Asenov
Intel’s triangular finfets suffer a severe performance disadvantage to rectangular finfets and a further disadvantage in respect to SOI finfets, says Professor Asen Asenov of Glasgow University who is the CEO of Gold Standard Simulations.
“Intel may have technological reasons for adopting this shape but by doing so you reduce performance by 12-15%,” Asenov tells EW.
In a paper on the GSS website, Asenov points out that, while Intel bulk FinFETs have 12%-15% less performance than equivalent rectangular bulk FinFET, compared to rectangular ‘bulk’ FinFETs, rectangular SOI FinFETs have either 5% higher drive current at equivalent threshold voltage and leakage, or 2.5 times less leakage at equivalent on current.
“Bearing in mind that it is easier to make rectangular SOI FinFETs than rectangular bulk FinFETs, moving from triangular Intel bulk FinFETs to rectangular SOI FinFETs can deliver approximately 20% performance improvement,” says Asenov.
Asked why he thinks Intel has adopted this disadvantageous shape, Asenov replies: “We have very little solid knowledge. Maybe there’s a technological reason associated with the deposition of HK gate dielectric over vertical walls.”
“IBM can make nice rectangular shaped vertical walls,” adds Asenov.
This could be a problem for Intel because IBM has licensed its technology to UMC, the No.2 foundry.
Meanwhile Gobalfoundries, the No.3 foundry, is preparing SOI technology.
“There has never been a time in my life, and I’ve been in this business for 35 years, when it’s been so exciting and so complicated,” says Asenov, “companies will have to decide on the different technologies and these will be very expensive decisions. It will also mean very difficult decisions for the fabless companies.”Tags: Asenov