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Cadence Design Systems is offering design for manufacture analysis for 28nm and 32nm process technologies in the latest release of its Encounter Digital Implementation (EDI) system-on-chip design tool.
The tool will be used for the design of high complexity SoCs with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
To address the design complexity issues of this class of device EDI System 9.1 combines automatic floorplan synthesis, data abstraction modelling and concurrent macro- and standard cell placement.
This is achieved in a process the company calls “design exploration” which involves the automatic examination of thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel.
“This exhaustive examination allows users to fully explore the range of design possibilities,” said Cadence.
“Since foundries mandate DFM checks in the physical design flow at 40nm and below, built-in, foundry-certified DFM analysis is a must-have at these nodes,” said Cadence.
An integrated DFM capability will offer pattern intelligence and filtering in the interconnect routing phase of the design process.