TSMC delivers 20nm double patterning reference flow
TSMC has delivered two 20nm foundry-first reference flows. One enables enables double patterning technology design using proven design flows. The other supports Chip On Wafer On Substrate (CoWoS) development.
EDA vendors’ tools are qualified to work with TSMC 20nm process technology by incorporating double patterning aware place and route, timing, physical verification and design for manufacturing.
The silicon-validated CoWoSreference flow enables multi-die integration to support high bandwidth, low power, fast time–to- market 3D IC designs.? The CoWoS flow allows designers to use existing, mainstream tools from leading EDA vendors.
“These Reference Flows give designers access to TSMC’s advanced 20nm and CoWoS technologies,” says TSMC vp for R&D, Dr. Cliff Hou,? “delivering advanced silicon and manufacturing technologies as early and completely as possible to our customers is a chief goal for TSMC and its OIP design ecosystem partners.”
TSMC’s 20nm Reference Flow enables 20nm design with double patterning technology (DPT) aware capabilities to reduce design complexity and deliver required accuracy. DPT enablement includes pre-colouring capability, new RC extraction methodology, DPT sign-off, physical verification and DFM. In addition, TSMC and its ecosystem partners design 20nm IP for DPT compliance to accelerate 20nm process adoption.
The CoWoSReference Flow enables 3D IC multi-die integration with a smooth transition to 3D IC with minimal changes in existing methodologies.
It includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.
The Custom Design Reference Flow enables DPT in 20nm custom layouts. It provides solutions to 20nm process requirements, including a direct link with simulators for the verification of voltage-dependent DRC rules, and integrated LDE solutions and handling of HKMG technology. RF Reference Design Kit provides new high frequency design guidelines. These consist of 60GHz RF model support, high performance Electromagnetic (EM) characterization that enables customer design capability through the examples of 60GHz front-to-back implementation flow and Integrated Passive Device (IPD) support.