The answer is in the power of the software running on a high performance hardware emulator.
Mentor has long maintained that emulation is the only way to verify complex system-on-chip (SoC) designs. Now it has introduced emulation techniques which address system-level verification challenges in complex SoC and system designs.
The EDA company calls the techniques “applications” but essentially they define the three main elements of the classic IC emulation cycle.
Starting with its Veloce in-circuit emulator (ICE), which is now deterministic, Mentor has defined two additional elements; a design for test function and a clocking optimisation function.
According to Eric Selosse, general manager of Mentor’s emulation business: “The focus on software apps for specific SoC and system-level challenges is driving the future of emulation.”
The deterministic ICE will be advantageous when emulating virtual systems, before silicon implementation, says Mentor. It will address visibility and debug issues in these virtual-based models.
Then before silicon tape-out, Veloce now includes a design for test (DFT) check as a final check for potential errors prior to tape-out.
For complex SoCs with multiple clocks a Veloce application called FastPath can be used to optimise the emulator with faster model execution speed.
The new apps will run on an upgraded Veloce OS3 operating system, which itself adds the capability to manage distributed high performance computing platforms for improved compile time.
At the gate-level the emulator now accepts flat or hierarchical designs. This can reduce the memory needed for compilation.
Mentor says this will make it easier to load and verify gate-level designs.
The emulator will run faster as well, says Mentor.
Mentor says it wants to show that software, running on a qualified hardware platform can target design risks more efficiently than hardware-centric design verification.