Fujitsu Batboard ADC IP evaluation kit

Fujitsu Microelectronics has introduced an evaluation kit called Batboard for its fast ADC IP, which is based on its Charge-mode interleaved sampler technology (CHAIS).

The kit allows early silicon characterisation of a two-channel 56GSamples/s 8-bit ADC using the single-chip Robin device (the first customer evaluation…

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ARM-based structured Asic gets IAR development support

Structured Asic supplier eASIC and embedded tool firm IAR Systems have announced the availability of the e926 development kit for designing ARM926EJ-based embedded systems.

The kit includes eASIC’s e926 development board, IAR Systems’ software design and debug tools, as well as AMBA peripherals and reference designs.

The e926…

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Prototyping audio designs in quick time

AMI Semiconductor is offering a route to quick prototyping of SoC designs with a module that features the BelaSigna 250 audio processor.

The BelaSigna 250 RPM comes as a complete digital audio processing system with an EEPROM, power supply regulation and passives integrated on a small form factor board.


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CMOS process gets low voltage threshold

Austriamicrosystems has extended its foundry technology portfolio with a low threshold (LVT) CMOS process option based on its proven 0.35µm analogue CMOS (C35) technology.

The LVT process option offers a set of 3.3V and 5.0V NMOS and PMOS devices with threshold voltages as low as 0…

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Standard cell Asic on 130nm process

AMI Semiconductor has announced availability of a 130nm standard cell Asic technology.

The Asic market is increasingly making use of 180nm process technologies, moving to 130nm as the mid-range technologies advance.  This represents 60 per cent of the designs being developed today, said the firm.

The 130nm standard cell…

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Structured Asic gets synthesis tool

NEC Electronics is offering customers of its ISSP structured Asic platform a six-month licence of Synplicity’s Amplify ISSP Pro physical synthesis software. Amplify software will be offered as part of NEC’s OpenCAD tool suite. For parallel design efforts requiring multiple design seats or for designs requiring an…

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SERDES slices for platform Asic

LSI Logic has added to its RapidChip structured Asic family new design options for high speed serial applications.   Available are up to 48 SERDES (serialiser/deserialiser) elements, up to five million gates and 3.7Mbits of RAM, based on the firm’s recently introduced MatrixRAM internal memory architecture. There is…

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EEPROM blocks write at 100µA

Austriamicrosystems says the embedded EEPROM blocks for its 0.35µm process mixed signal Asic family offer low power operation and high data retention over an extended temperature range due to its PMOS-based NV technology.

  The EEPROM blocks contain a bus interface and internal charge pump. The NV process…

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