Asics News and Updates

Imagination announces IoT radios

Imagination Technologies has announced the first of its Whisper Series5 radio baseband processors, which it calls radio processing units (RPUs). Available as intellectual property for integration into SoCs, there are versions for 802.11n Wi-Fi, Bluetooth Smart, or both. The cores are designed for low power consumption, and applications…

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SERDES slices for platform Asic

LSI Logic has added to its RapidChip structured Asic family new design options for high speed serial applications.   Available are up to 48 SERDES (serialiser/deserialiser) elements, up to five million gates and 3.7Mbits of RAM, based on the firm’s recently introduced MatrixRAM internal memory architecture. There is…

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EEPROM blocks write at 100µA

Austriamicrosystems says the embedded EEPROM blocks for its 0.35µm process mixed signal Asic family offer low power operation and high data retention over an extended temperature range due to its PMOS-based NV technology.   The EEPROM blocks contain a bus interface and internal charge pump. The NV process…

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Asic sees cost benefits on 0.15µm

AMI Semiconductor has moved its “lower entry cost” Asic platform to 0.15µm process technology. The second generation of its XPressArray structured Asic family, which is based on a programmable metal design approach to reduce cost, is intended as an alternative for some FPGA designs which can be cost…

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IDE for structured Asic designs

Cambridge Consultants has a generic integrated development environment (IDE) for structured or platform Asic design. Called xIDE, it is available in both UNIX/Linux and Windows versions and so custom plug-ins can be created for a range of embedded processors, IP cores, and interfaces. The customised xIDE can be…

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Asic interface for QDR-2

LSI Logic has introduced a high speed physical layer interface to QDR-2 SRAM memory, aimed at high-end network routers, switches and host bus adapters. Supporting speeds up to 333MHz and 667Mbit/s, the QDR-2 Asic core is a physical layer interface with a special HSTL I/O…

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DDR-2 interface is prevalidated for Asics

LSI Logic has introduced a physical layer memory interface the DDR-2 Asic core which is the firm’s first physical layer interface and I/O buffer to support 333MHz/667Mbit/s data speeds. The DDR-2 core with SSTL18 I/O interface buffer has pre-verified functionality, layout and…

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