Key steps were designing to the performance sweet spot of GUC’s DDR2/3 high speed interface IP, a condensed package substrate, and a PCB through a precise DDR system simulation flow and measurement correlation.
The consumer electronics marketplace for this particular ASIC is mature so both performance and cost are equally paramount.
Cost was reduced by the mature 40nm process, a cost-reducing PCB and a four layer substrate.
Performance would be determined by retaining the speed characteristics of DDR 2/3 interface and optimizing system integration.
While cost-effect, the four layer substrate and cost-reducing PCB limit the performance and production margin of the DRAM read/write rate, so the GUC DDR 2/3 IP performance on the 40nm low-power process was very critical to system performance.
The GUC DDR 2/3 high speed interface IP were implemented with a low jitter clock scheme and high performance memory I/O design that pushed the operational speed 10%-15% beyond the published limits.
GUC engineers enhanced the performance through a customized system chip, package, broad simulation flow covering, signal and power integrity analysis and silicon measurement correlation.
“The most interesting thing about this challenge is that required the ingenuity of both IP and systems engineering,” said Jim Lai, President of GUC. “The complexity of the business and technology challenges created a complexity that required innovative thinking and execution on a number of levels,”