Developed jointly with wireless networks firm Flexibilis Oy, the IEC 62439-3-compliant reference design includes Flexibilis Redundant Switch (FRS) intellectual property implemented on a Cyclone-class FPGA or Cyclone V SoC.
The reference design implements mission-critical communications systems in smart grid substations.
“A key trend today in developing a smarter power grid is bidirectional communication and real-time control of the equipment in the grid’s transmission and distribution substations,” said Jason Chiang, senior strategic marketing manager in Altera’s Industrial Business Unit.
The Flexibilis HSR/PRP IP included in the reference design is a triple-speed 10/100/1000Mbit/s Ethernet Layer 2 switch that is scalable from 3 to 8 ports and is compliant with the IEC 62439-3 standard.
The IP is optimised for use on the Cyclone IV FPGA, Cyclone V FPGA or Cyclone V SoC, with their dual-core ARM Cortex-A9 processor subsystems.
Cyclone V SoCs enable customers to reduce component costs by implementing their HSR/PRP switch along with the associated software stacks running on the ARM processor subsystem in the FPGA.
For timing synchronisation, the HSR/PRP solution supports IEEE 1588 Precision Time Protocol (PTP) Version 2.
Altera and Flexibilis are showing the FPGA-based HSR/PRP reference design in Altera’s booth at Embedded World 2013.
“The IEC 62439-3 standard is rapidly evolving, making the flexibility of an FPGA an ideal platform to base our FSR IP on,” said Heikki Ala-Juusela, chairman of the board at Flexibilis.