The board enables both x1 and x4 endpoint evaluation and design, and includes a variety of demo executables – a basic demo for control plane applications, a throughput demo for high-bandwidth applications, a colour bar demo and an image transfer demo.
There is also a 60 day software tools license, x1/x4 endpoint IP core, and scatter-gather DMA IP core.
“Users typically can achieve working PCI Express hardware in thirty minutes, and a known good starting point for a design in less than two hours,” claimed the firm.
Both Windows and Linux versions are available.
There are five ECP3 FPGAs, all toggling at 1Gbit/s, with embedded memory of up to 6.8Mbit, logic density from 17k to 149k LUTs (look-up tables), and up to 586 user I/Os.
They have multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and cascadable DSP slices aimed at RF, baseband and image signal processing.