Altera adds hard floating point to FPGAs

Altera is shipping Arria 10 FPGAs with hardened floating-point DSP blocks, but customers will have to wait for design flows.

The DSP block, which is IEEE 754-compliant, will also be in Stratix 10 FPGAs.

Up to 1.5 Tflop is claimed in Arria and 10 Tflop in Stratix…

Read More

Lattice offers 3.25Gbit/s SERDES in low power FPGA

Lattice Semiconductor has announced its ECP5 family of small form-factor FPGAs for small-cell basestations and microservers.

These small devices use small LUT4 based logic slices with enhanced routing architecture, dual-channel SERDES to save on silicon area.

Lattice’s approach is to offer small form-factor (10mm x…

Read More

VadaTech adds 100G processor to Xilinx modules

VadaTech has released a suite of Xilinx FPGA mezzanine card modules cocvering Virtex-5, Virtex-6, Artix-7, Kintex-7, Virtex-7 FPGAs and Zynq All Programmable SoCs.

A Virtex-7 device is used for a 100G processor with an integrated FPGA in the double-module AMC size.

The single…

Read More

FPGAs can secure IoT devices, says Microsemi

Embedded microprocessor designs can benefit from safe and secure boot-up code by making use of the trusted boot-up code held in an FPGA.

A secure boot reference design from Microsemi uses the security features in its SmartFusion2 SoC FPGAs to securely boot any application processor in an embedded…

Read More

Avnet offers Rohm power supply for Zynq-7000

Avnet has partnered with Rohm Semiconductor to develop a power supply module board specifically for Xilinx 7 series FPGAs and Zynq-7000 all programmable SoC’s evaluation kits.

Rohm’s power supply module is used with the Avnet-designed Mini-Module Plus Development System.

Based on the BD95601MUV/BD95602MUV power…

Read More

Altera speeds up FPGA compile times

Altera claims the latest version of its Quartus II FPGA design software will cut compile times by 30% on average compared to the previous version.

In some cases compile time can be cut by up to 70% through algorithm optimisation and increased parallelisation, said Altera.

The software also includes the…

Read More

Lattice adds sensor control to tiny low power FPGA

Lattice Semiconductor has added new hardwired IP functions to its iCE40 range of low power and low density FPGAs.

A new smaller package size is 1.4mm x 1.48mm x 0.45mm.

The iCE40LM FPGAs have hardwired IP for strobe generators, I2C and SPI interfaces.

The FPGAs with active…

Read More

Cypress reduces power consumption in PSoC range

Cypress Semiconductor’s latest PSoC 1 programmable system-on-chip device has been optimised for low power with a 1.1µA standby mode and 100nA deep-sleep mode.

The CY8C24x93 PSoC 1 devices come in multiple small-footprint packaging options, including a 3×3 mm2 QFN package.

The devices integrate…

Read More