Xilinx launches 20m ASIC gate stacked silicon FPGA
The world’s largest programmable device uses 2.5D stacking to put four FPGA die aligned side by side on a silicon interposer. The interposer includes over 10,000 high speed interconnects between each die.
“It’s a nail in the coffin of ASICs,” says Liam Madden, corporate vice president for FPGA development and silicon technology at Xilinx, “from an economic basis it no longer makes sense to make ASICs.”
“For every engineer designing RTL there are two to three engineers verifying,” adds Madden, “ASIC takes two years, FPGAs take under one year.” Moreover, the NRE on a 28nm ASIC is $50m, according to Xilinx.
Asked why the ASIC vendors couldn’t follow suit with a 2.5D stacked silicon approach of their own, Xilinx CEO Moshe Gavrielov, explains that others may not be able to follow the approach quickly.
“We think we have the right architecture and the tool flow to support it,” says Gavrielov, “we provide the tools that enable it, and that’s a big deal. If you have to go out and beg for the tools, that’s not attractive.”
The 28nm stacked die device, called Virtex-7 2000T FPGA, has been five years in the cooking at Xilinx. In most applications it needs nothing more exotic than a heat sink to cool it.
“The new device underpins a flexible, yet targeted, emulation architecture and delivers a significant capacity improvement, allowing us to more easily run complete system verification and validation for our next generation processors,” says John Goodenough, vice president design technology and automation at ARM.
The device will also be useful in accelerating the prototyping and emulation of ASIC systems.
The device is built on TSMC’s 28nm HPL (low power with HKMG) process to deliver FPGAs with less static power.Tags: asic, Xilinx