ARM reveals more details of Cortex A5 processor

ARM has developed its Cortex-A5 processor for the smartphone market, following on from the ARM9 and 11.


Compared on the same process, according ARM figures, the A5 uses 80% less power than the firm’s ARM11, its current smartphone processor, and delivers 20% more processing, while needing 33% less silicon area.

It has the same silicon area as the ARM9, used in entry-level phones, and can deliver 80% more processing.

“If a phone maker is using an ARM9 now in a low cost phone, it can switch to a Cortex-A5 and add Internet capability,” ARM director of programme management John Goodacre told EW.

How did ARM get so much more from the same silicon?

“The short answer is that we have learned a lot designing the Cortex-A8 and A9,” said Goodacre.

The slightly longer answer is: improved branch prediction and improved instruction issue.

The firm is releasing DMips figures, but prefers to use the Embedded Microprocessor Benchmark Consortium’s (EEMBC) CoreMark. 

“We find Dhrystone Mips are being abused in the industry,” said Goodacre.

A quad-core A5 delivers 8.5 CoreMark/MHz, and 10 CoreMark/mW – both on TSMC’s 40nm general purpose process.

A single core A5 can do everything a top-end smartphone requires,” said Goodacre. 

As ARM-dominated phones get smarter and x86-dominated notebooks get smaller, ARM is on the verge of competing directly with Intel’s Atom processor.

“The Atom CPU would need to be manufactured at 15nm to match the silicon area of the Cortex-A5 in today’s 45nm process,” claimed ARM.

CoreMark for CoreMark, Goodacre calculated that a dual-core A5 at 1GHz would match or just beat an Atom N270 at 1.6GHz.

The recently announced Cortex-A9 can, at 800MHz according to ARM, match a 1.6GHz Atom N270 in performance at one fifth the power consumption.

The A5 and A9 are binary-level compatible. “For the first time we have taken compatibility down to the operating system level,” said Goodacre.


Both processors get ARM’s ‘snoop control unit’ which reduces multi-core bus-clash drawbacks by transferring data directly at the L1 level, prevent the cores being interrupted.

Also on the A5 is the TrustZone security block which get used for protecting keys in phones and can be applied to applications such as banking, and the
Neon SIMD media processor for video decode, video encode, and 2D acceleration.

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