The 2GHz processor was implemented on a 28nm-SLP (Super Low Power 28 nanometer High-K Metal Gate) process.
The Cortex-A12 processor is the higher performance succssor to ARM’s Cortex-A9 smartphone processor.
According to Dipesh Patel, executive vice president and general manager, physical design group, ARM, it is significant that the 28nm test chip utilised ARM POP IP, this “will accelerate its time to market.”
This is the first POP IP offering for the Cortex-A12.
ARM POP technology is intended to make hard processor core implementation and performance more predictable. The processor firm likes to refer to it as “core hardening” for its CPUs.
The technique invloves the use of Artisan Physical IP standard cells, logic and memory cache optimised for the process technology.
ARM assists the chip fabricator with optimised floor plans, scripts and design utilities. There is also detailed performance benchingmarking to help the foundry.
Cadence’s RTL-to-signoff digital implementation flow was used, including Encounter RTL Compiler, Encounter RTL Compiler with Physical, Encounter Digital Implementation System and Encounter Conformal Equivalence Checker.
“We collaborated closely with Cadence and ARM to implement this new core using our 28nm low-power process, and ARM libraries specifically tuned to meet demanding mobile market requirements,” said Ana Hunter, vice president of product management at Globalfoundries.