Renesas says multiple process technology is key for MCUs

Guest columnist Graeme Clark, product marketing specialist at Renesas Electronics Europe says the implementation of microcontrollers on multiple process technologies extends performance and applications

With the design of modern microcontrollers being based on a modular design methology, it has become easier to use the both the same CPU and peripheral design on multiple semiconductor processes.

The use of multiple process nodes to change the characteristic envelope of microcontrollers allows the production of highly optimised devices with specific performance characteristics aimed at a specific range of applications. The RX family of 32-bit CISC ( Complex Instruction Set  Computer ) microcontrollers from Renesas is a perfect example of this, using the advanced MONOS (metal-oxide-nitride-oxide-silicon )  embedded flash technology on multiple process geometries to provide solutions for a number of different applications.

The 32-bit CISC RX  is currently implemented on two new MONOS flash process technologies, giving two discrete performance envelopes, providing users with a choice of operating parameters.

MONOS technology is a highly reliable flash technology, with almost 20 years of production history and has been used in millions of microcontroller and memory products. 

The main feature of the MONOS Flash technology is the use of an electron trap rather than a floating gate to hold the charge required to indicate whether the contents are a logic “one” or “zero”.

The use of an electron trap means that in case of a defect, rather than all charge carriers on a floating gate draining away, resulting in the complete failure of the flash cell, only those at the defect location are drained. This accounts for a considerable increase in reliability compared to conventional Flash technology. This means that MONOS technology can be used to manufacture extremely cost effective and reliable microcontrollers, with very large embedded flash memories

The use of more advanced processes also result in smaller cell size,  offering higher access speeds, resulting in read access time of down to 10ns or less .

The figure shows the MONOS Flash cell structure in comparison to conventional NOR Flash. The charge carriers on the floating gate determine whether a logic one or zero is stored. In a conventional flash cell, the floating gate is conducting and therefore all charge carriers drain away in case of a leak in the oxide layer.

MONOS Flash technology does not suffer from this problem, it features a Charge Storage Layer made of a non-conducting nitride layer (Si3N4), effectively solving this problem. This means that MONOS flash technology can also offer very high write-erase counts, with up to 100k write-erase cycles.

The read and write voltages and especially the flash cell’s threshold voltage (Vth) are also crucial technology parameters. Due to the MONOS Flash cell structure, reading is performed at the low voltages used by the core logic. As a consequence, cell control logic and word-line-drivers (WL)  is made using fast core-MOS technology without special high voltage logic. This minimises the need for on chip charge pumps to generate high voltages for read operations, thus saving space and cost, and enabling both high speed reading and low voltage operation. Low voltages and the avoidance of large on-chip charge pumps also helps to lower the power consumption of the device.

MONOS technology is already available at different process nodes, ranging from 90 nm to 180 nm, each of which can be optimised with different performance characteristics. MONOS Flash technology provides a perfect platform for the development of  a wide range of  microcontrollers addressing a range of different applications requiring different performance characteristics.

One of the first implementations of a microcontroller using MONOS technology, has been designed to address applications needing a fast CPU and high levels of on-chip memory and peripherals integration. Due to these requirements, the most suitable process was the 90nm MONOS Flash process.

This flash process provides for a 10 ns flash access time, allowing for 100 MHz single cycle flash operation. The use of the 90nm process also allows the implementation of up to 2 Mbytes of on chip flash memory and 128 kbytes of on chip SRAM and the integration of complex peripheral functions, such as Ethernet, USB and CAN interfaces and motor control timers.

While the use of a 90 nm process allows the design of extremely high performance products, there is another class of application with much tougher demands on power consumption and operating voltage.  The 90 nm MONOS flash process does not meet these requirements, however a low power, low voltage 130 nm MONOS flash process provides the ideal technology to address these applications.

The 130 nm process trades off performance and maximum memory size, for much lower active, RTC mode (Real Time Clock/Calendar operating) and standby mode power consumption.

This second implementation of core on the 130 nm MONOS Flash process is ideal for these low power applications. This device is compatible at binary level and provides a much wide operating voltage range, 1.62 – 5.5v operation with lower power consumption. 

The use of multiple process technologies allows the user to standardise on one standard CPU Core Architecture to meet all their application requirements. In addition the use of the same design rules for each of these implementations also means that many of the peripherals and features are common across these devices, resulting in common software and development tools.

In the future additional process technologies will come into use, allowing the development of additional processor families using a standard core design.  These will allow the development of devices offering higher levels of CPU performance and larger flash memory configurations as well as offering a range of new device characteristics, while maintaining compatibilit y with the other members of the family.

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