The paper described a low power DSP device capable of running at 0.6V.
“The design of a low-voltage processor in 28nm requires a system-level approach – from optimising the circuit styles and memories to the development of a custom low-voltage timing flow,” said Anantha Chandrakasan, MIT professor and pioneer in the area of low-power design.
“This chip demonstrates an aggressive low-power methodology to ensure robust low-voltage and ultra-low-power operation for a smartphone application processor,” said Chandrakasan.
It described a way of addressing the design issues of very low power DSP operation. At low voltages in deep submicron process nodes, within-die random variation in transistor threshold voltage can cause circuits to have functional failures.
There is also a static timing issue. The delay distribution of standard cells at low voltages is no longer a Gaussian random variable.
“Traditional SSTA tools based on a Gaussian distribution can suffer from 10-70% underestimation of delay at 0.6V,” said the TI paper.
The paper said a statistical static timing analysis technique can improve the accuracy of design timing at very low voltages to less than 8%.
The ability to accurately analyze low-voltage timing avoids excessive design margins and minimizes impact to area and high-voltage performance.