It is a sign of the trend to use sophisticated equalisation and clocking to operate over lossy channels without consuming too much power.
Developed by LSI Logic, the transceiver covers CEI-25G, CEI-28G, IEEE802.3bj, and 32G-FC standards.
“In a previous ISSCC, a 28Gbit/s transceiver over 29dB channel consuming 700mW in 32nm CMOS was reported,” said IEEE wireline communications chair Daniel Friedman. “This is a longer reach and lower power 28Gbit/s transceiver in 28nm CMOS.”
The design’s analogue front-end provides 15dB of boost, while the digital front-end uses a half-rate 1-tap unrolled architecture. Over a 34dB test channel, the horizontal eye margin is 0.49UI and the vertical margin is 99mV.
ISSCC paper 2.1 ‘28Gbit/s 560mW multi-standard serdes with single-stage analogue front-end and 14-tap decision-feedback equaliser in 28nm CMOS‘
Meanwhile, a team from National Taiwan University and Atilia Technology, both of Taipe, presented the first fully integrated 60Gbit/s transmitter in CMOS. The non-return to zero (NRZ) transmitter consumes 450mW of power and the PAM4 transmitter consumes 290mW, both from a 1.2V supply. A 60+Gbit/s receiver digital front-end in 65nm CMOS was presented at ISSCC 2013.
ISSCC paper 2.3 ‘60Gbit/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS‘.
Also amongst the wireline communications papers, Broadcom described a 40nm CMOS 4x28Gbit/s transceiver for 100GbE and 40GbE. The transmitter has a three-tap FIR with output-phase adjustment, and the receiver uses a half-rate CDR with a dedicated eye-monitor channel.
Dissipation is 780mW from 0.9V, and it achives <10-15 bit error rate over a 20dB-loss channel at Nyquist.
Wireline communications seem to give universities a chance to show off their capabilities.
Consuming only 5.8mW from 1V, UCLA presented a 25Gbit/s receiver that includes a one-stage continuous-time linear equaliser and a half-rate/quarter-rate two-tap digital front end. The design is fabricated in 45nm CMOS and uses charge-steering techniques to equalize for a Nyquist channel loss of 24dB. Eye opening is 0.4UI for <10-12 BER, and it includes 4x demultiplexing.
Not to be out done, Oregon State University’s 16Gbis/s 3-tap 65nm CMOS digital front end uses a charge-based sampling circuit and can operate down to a 0.7V. It gets 0.46UI margin at <10-12 BER over 18dB of channel loss, using 0.25pJ/bit.
Korea’s Pohang University of Science and Technology (POSTECH ) described DLL-based reference-less clock data recovery (CDR) for intra-panel interfaces. Pattern-dependent clock embedded signalling allows clock information to be transmitted with an overhead of only one bit for each data packet. Implemented in 65nm CMOS, the recovery circuit achieves 0.63mW/Gbit/s (at 9Gbit/s).
The same university introduced a coefficient-error-robust transmitter architecture using channel loss to suppress the impact of coefficient errors. In 65nm CMOS, it operates at 8Gbit/s over a 17.5dB-loss channel and, at the expense of 27% more area, improves the eye variation by more than 2x compared with a conventional feed-forward equaliser, said the IEEE.
UC Berkeley, with Xilinx, described a 16GHz injection-locked 20nm ring oscillator employing pulse-position modulation to cut flicker noise through feedback control. “Compared to conventional injection-locking, jitter reduces from 434 to 268fs(subscript rms). The circuit consumes 46.2mW and covers 0.044mm2.
From Italy, Politecnico di Milano discussed a technique to control the bandwidth and frequency response of a digital phase-locked loop (PLL), ensuring loop bandwidth remains independent of analogue parameters without injecting extra signals into the loop. Embedded in a 65nm CMOS bang-bang 2.9-4.0GHz PLL, it sets the bandwidth up to 2MHz with 4% accuracy, independent of input noise.