Described at ISSCC, the team used 28nm ultra-thin body buried-oxide (UTBB) fully-depleted silicon-on insulator (FD-SOI) technology, which also allows operation over a wide voltage range.
“The device, produced by ST on their 28nm UTBB FD-SOI process, allows body-bias-voltage scaling from 0 to 2V [see below], decreases minimum circuit operating voltage and supports clock-frequency operation of 460MHz at 400mV,” said Leti. “The demonstrator achieves unprecedented levels of efficiency in voltage and frequency using a combination of design techniques. ST and Leti developed and optimised standard cells libraries over 0.275 to 1.2V. Among the cells, fast pulse-triggered flip-flops are designed for variability tolerance at low voltage.”
On-chip timing-margin monitors dynamically adjust clock frequency to a few per cent of the maximum operating frequency, whatever the supply-voltage, body-bias-voltage, temperature, and process variables, said the lab.
In many ways, SOI is an alternative to finFET technology as a way to get good performance from transistors between 22 and 10nm (or wider, nomenclature between companies varies). The wafers are more expensive, but the process is cheaper.
Uniquely, SOI allows ‘body biasing’ – throttling performance independent of the supply voltage by varying a potential between the underlying substrate and the silicon above the buried oxide – in this case from 0V to 2V.
A feedback loop can be established to get the best speed out of any particular supply voltage by servoing the bias voltage.
ISSCC 2014 paper: ‘A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding Fmax tracking’.