“The methodology is universal for many kinds of structures,” says researcher Xi Ling. “This offers us tremendous potential with numerous candidate materials for ultra-thin circuit design.”
The technique also has implications for the development of ultra-low power, high-speed tunnelling transistors and the integration of optical components.
Normally, only materials with closely matched crystal lattices have been deposited laterally in the same layer of a chip.
The researchers’ experimental chip, however, uses two materials with very different lattice sizes: molybdenum disulfide and graphene, which is a single-atom-thick layer of carbon.
Moreover, the researchers’ fabrication technique is generalised to any material that, like molybdenum disulfide, combines elements from group six of the periodic table, such as chromium, molybdenum, and tungsten, and elements from group 16, such as sulfur, selenium, and tellurium.
To assemble their laterally integrated circuits, the researchers first deposit a layer of graphene on a silicon substrate. Then they etch it away in the regions where they wish to deposit the molybdenum disulfide.
Next, at one end of the substrate, they place a solid bar of a material known as PTAS. They heat the PTAS and flow a gas across it and across the substrate. The gas carries PTAS molecules with it, and they stick to the exposed silicon but not to the graphene. Wherever the PTAS molecules stick, they catalyse a reaction with another gas that causes a layer of molybdenum disulfide to form.