Surrey University unveils nanotransistor theory

Researchers at the University of Surrey and Hitachi in Japan have established further design constraints for their high-performance thin-film transistors, unveiled earlier this year.

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Researchers at the University of Surrey and Hitachi in Japan have established further design constraints for their high-performance thin-film transistors, unveiled earlier this year.

The transistors are polycrystalline silicon and conduct well, but are far less leaky than conventional types because the channels are only a few nanometres thick.

“With thin channels, the quantum confinement effect dominates and the bandgap of the material becomes wide so leakage current decreases,” researcher Dr Xiaojun Guo told Electronics Weekly at the time.

Crystals in the material are made by slow chemical vapour deposition and are so small, only around 10nm across, that the material is known as nanocrystalline silicon.

Initial devices were deposited on 200mm silicon wafers and Guo sees no problems in making them on glass as deposition temperatures are low.

Traditional mathematical FET models are almost useless and the group has been improving its theoretical grasp of the technology, as well as looking for limitations to the beneficial effects of channel thinning – which it has found.

Hundreds of otherwise identical transistors were fabricated with varying channel widths and thicknesses.

All channels were 500nm long, with widths varying in seven steps between 70 and 500nm, and thickness of 2, 2.5 or 3nm.

Experiments showed that transistors with 3nm channels have good FET characteristics whatever the width.

But device-to-device characteristic variations, and individual device characteristics, get progressively worse in 2.5 and 2nm transistors as the channel is narrowed below 300nm.

In short, good transistors can only be made predictably if the channel is at least 3nm thick, or at least 300nm wide.

Modelling and experimental work has uncovered the reason.

The channels look very much like crazy paving as they are assembled from flat irregular crystal grains – on average 10nm across and 2-3nm thick.

Individual grains are non-conductive with no gate bias, and conductive above a certain gate potential.

Subtle variations in grain thickness, grain-to-grain crystal alignment, and other factors, mean some turn on before others.

To get conduction all the way from source to drain there has to be a continuous row of adjacent ‘switched on’ crystals.

Modelling shows that at the point of conduction a snake-like meandering line of conducting crystals has formed – a so called ‘percolation path’.

Statistical analysis, claims Guo, shows the snakes are statistically more likely to reach from source to drain in wider channels.

In narrow channels, potential percolation paths are more likely to hit the non-conductive edge of the channel and go no further. Surrey describes these potential paths as ‘pinched-off’.

With 10nm crystals and a 500nm long channel, the knee in the curve is at 300nm wide.

The thickness of the channel appears to affect characteristics simply because random thickness variations are the same for 2nm and 3nm grains, but as a percentage of thickness are more profound in thinner grains – resulting in a wider spread of grain-to-grain threshold voltage in thinner grains.

3nm grains are thick enough for variations in threshold voltage to be minimal. These two effects taken together, said Surrey, explain why the device threshold of 70nm wide/2.5nm thick transistors can be anywhere from a few mV to 4V, and the spread for 150nm/2nm transistors is 2-9V.

3nm transistors have a spread of only a few tens of mV down to, and probably beyond, 70nm.

2.5nm transistors are predictable to 200nm, and 2nm transistors are fairly well controlled at 300nm, but only really good at 400nm wide.

The devices were first fabricated by Hitachi and used for low power memory design. “We built collaborations with Hitachi after that, and focus on the characterisation and modelling of the devices, and the idea of using the technique to design high on-off ratio transistors for large area electronics,” said Guo, who works at Surrey’s Advanced Technology Institute (ATI).


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