The technique allows chips to be stacked on top of each other with circuit interconnections provided by the through-silicon vias (TSVs).
TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits.
Chip stacking is being viewed as an alternative to node scaling at the transistor level, but there are manufacturing challenges.
Globalfoundries’ approach to the challenege of chip stacking is to use a “via-middle” technique in TSV integration, inserting the TSVs into the silicon after the wafers have completed the front-end of the line (FEOL) flow and prior to starting the back-end of the line (BEOL) process.
“This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material,” said the foundry.
To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, it has developed a proprietary contact protection scheme.
It demonstrated SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.
“Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality,” said David McCann, vice president of packaging R&D at Globalfoundries.
“Our next step is to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain,” McCann.