AMD previews next-generation microarchitecture
Framed by the mounting challenge of delivering increased customer value with higher performance while keeping the lid on power requirements, Advanced Micro Devices senior fellow Chuck Moore offered a peek at his company’s ninth generation microarchitecture during a keynote address at the In-Stat Spring Processor Forum.
“This industry is dependent on customer value,” said Moore, “so the question becomes how do we continue increasing customer value? While we could design things faster and faster they consumed more power… it wasn’t just about the core, but about the entire package.”
Modularity and flexibility also became more important as time to market became a greater concern, Moore said. And virtualisation and increasingly diverse workloads added to the mix, making it imperative for companies to broaden their system-level focus going forward.
Within that framework, Moore did not miss the chance to find shortcomings with Intel’s microarchitecture and system design, pointing out bottlenecks and power inefficiencies – a tack also taken by Intel executives referring to AMD’s chips.
Even with Intel’s new Core microarchitecture, which the larger company announced at its Developers Forum earlier this year, the total system power required for Intel’s chip still remains about a third higher than that required for AMD’s chip, said Moore.
In that context Moore shared the areas AMD has focused on for its next refresh of its own microarchitecture. The company targeted six areas – scalable performance and balance, maintenance of performance per watt leadership, performance on diverse workloads, compatibility, enhanced virtualisation and enhanced RAS. This new microarchitecture will be delivered in the first half of 2007.
To increase scalability of its performance AMD has added faster HyperTransport links up to 5.2GT/s and an on-chip L3 cache shared by each of the multiple cores. The L2 cache remains private to each core.
“We believe this strikes the right balance,” said Moore.
AMD’s power-per-watt strategy relies upon independent and separate power management for the Northbridge and for the CPU. In addition, the microarchitecture uses independent CPU P-state and C-state controls for each CPU core.
To achieve performance on diverse workloads AMD enhanced its IPC on CPU core, adding support for 48 bit virtual and physical address space, large-page support and platform-level support for co-processors.
For compatibility AMD has incorporated DDR2 memory support with migration to FBDIMM generation 1 and generation 2 at the appropriate time, Moore said.
“We won’t force it to be used until customers want it,” he said. In addition, Hypertransport 1 will be backward-compatible.
Plans also call for enhanced virtualization, including I/O virtualisation and nested paging support. AMD’s enhanced RAS plans include memory mirroring, data poisoning support and Hypertransport retry protocol support.