IBM claims to make “first fully functioning” graphene IC

IBM graphene RF receiver

IBM graphene RF receiver

IBM says its researchers have created what it calls “a fully functional integrated circuit made of wafer-scale graphene”.

Graphene is a semicodnmcutor material which is being heavily touted as the key development for future very high speed ICs, and is particularly suited for wireless communications devices.

Graphene is one of the thinnest electronic nanomaterials and consists of a single layer of carbon atoms packed in a honeycomb structure. It possesses outstanding electrical, optical, mechanical and thermal properties that make it potentially less expensive and more energy efficient in device applications.

But the fabrication of a IC is a big challenge because the atomic dimensions of a sheet of graphene can be easily damaged during the fabrication flow of conventional integrated circuits.

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IBM first demonstrated a “proof-of-concept” analogue graphene integrated circuit in 2011, but performance was degraded due to the harsh fabrication processes.

The researchers have taken a new approach which IBM said is closer to mainstream silicon CMOS manufacturing processes. This was used to produce a multi-stage graphene RF receiver with what IBM called “big performance” gains.

“This is the first time that someone has shown graphene devices and circuits to perform modern wireless communication functions comparable to silicon technology,” said Supratik Guha, Director of Physical Sciences, IBM Research.

IBM said it has reversed the conventional silicon IC fabrication flow, “leaving graphene transistors as the last step of integrated circuit fabrication, which preserves graphene device performance”.

The multi-stage graphene RF receiver integrated circuit consists of 3 graphene transistors, 4 inductors, 2 capacitors, and 2 resistors.

All circuit components are fully integrated into a 0.6 mm2 area and fabricated in a 200 mm (or 8 inch) silicon production line, showing the unprecedented graphene circuit complexity and highest silicon CMOS process compatibility. The new approach also enables the possible heterogeneous 3D integration with a silicon CMOS backbone.

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