IEDM: Deeply depleted channels run SRAM at 0.425V
By replacing conventional mosfets with DDC transistors in an existing SRAM design, while using the same mask set, nominal operating voltage dropped from 1.2V to 0.9V, and power from 840µW to 170µW.
Minimum operating voltage might have been lower.
“The tester stopped at 0.425V,” SuVolta marketing v-p Jeff Lewis told Electronics Weekly.
SuVolta’s intellectual property, called deeply depleted channel (DDC), allows the distribution of transistor threshold voltages across a chip to be tightened significantly, without moving away from standard bulk-silicon techniques, claims the firm.
In Fujitsu’s 576kbit SRAM, Vth variation was halved.
Narrowing threshold spread, in turn, allows the operating voltage of the chip to be reduced before outlying high-threshold transistors get unacceptably slow.
An additional benefit, according to SuVolta, is that fewer outlying low-threshold transistors means less leakage – hence Fujitsu has achieved power reduction beyond simple voltage scaling.
What causes Vth spread in CMOS below 90nm is that there are so few dopant atoms in the channel that a handful more or a few less makes a significant difference to device characteristics.
With a depleted channel, there are no dopant atoms in the channel, removing that source of variation.
Instead of doping the channel, other structures are needed to make the transistor work (see diagram), but according to Lewis existing chip designs can be converted.
“It is cost neutral, you add some layers and you take some away”, claimed Lewis. Although logic will be the same, “you will probably have to re-tune the analogue”.
When ‘high-voltage’ transistors are required – for IO for example, the implant step (see diagram) can be missed off under those devices, he added.
A layer within a DDC transistor tunes its threshold voltage – allowing transistors to be either fast or power-saving. Up to four threshold levels are practical on a chip, said Lewis, and the ‘body’ of the structure is electrically accessible for on-the-fly Vth scaling.
SuVolta sees itself as competing with finFETs and advanced silicon-on-insulator (SOI) at 65nm and below – Fujitsu used 43nm channels and “we have a little bit of data at 28nm. I can’t say with who”, said Lewis.
“Successful reduction of random dopant fluctuation has been reported using two exotic structures, ETSOI and tri-gate finFETs. However, both ETSOI and finFETs are complex, making them difficult to match with existing design and manufacturing infrastructures,” claimed SuVolta. – ETSOI is extremely thin silicon-on-insulator.
“If you want the highest performance microprocessor, you probably want finFET,” added Lewis. “If you want SoCs with lower power, you probably want DDC.”
SuVolta’s DDC transistor on Fujitsu Semiconductor’s planar bulk silicon low-power CMOS process
The bottom grey layer is the substrate.
Implanted doping of the substrate forms the screening region (dark green) which screens the charge, sets the depletion layer depth, and serves as a body for dynamic Vth adjustment through biasing.
Next comes the epitaxially-grown Vth-setting offset region which pre-sets transistor threshold voltage levels, without degrading channel mobility and improving sigma Vth over conventional transistors, claims SuVolta.
On top of this is the undoped or very lightly doped channel region. The dashed green line simply separates SuVolta technology from a conventional gate stack.
576k SRAM macro yield as a function of supply voltage, with yield calculated by counting macros in which all bits have passed
Block count plotted against leakage