IEDM: Hollow through-silicon vias ease expansion issues

IBM is partially-filling through-silicon vias (TSVs) to side-step potential stress problems created when TSVs are completely filled with copper.

TSVs are a key technology for stacking chips directly on top of one another to fit multiple die into a single package.

“They are holes running vertically through the stack, filled with copper to interconnect all the levels,” said the IEEE. “A problem with TSVs is that copper and silicon expand with temperature at different rates, generating potentially damaging physical stresses.”

They also can cause deleterious proximity effects, and their fabrication processes can cause damage as well.

The IBM team has, for the first time, created annular – hollow cylindrical – copper TSVs to minimises these issues.

They were used to connect upper-level wires in a functional 32nm SOI 3D embedded memory module consisting of a 128Mbit DRAM on top of a 96Mbit DRAM, both of which employed 0.039 µm2 high-K/metal-gate technology.

“Extensive thermal cycling [>500 cycles] and stressing [>275°C for 1,500 hours] was performed with no loss of physical integrity or performance degradation due to the 3D technology,” said the IEEE.

itemid-54803-getasset.jpg BEOL – back-end-of-line

itemid-54804-getasset.jpgCross-sections of a module with a top die stacked face-to-face on a thin bottom die and assembled on an organic laminate with lead-free CFs (32nm).

IEDM paper 7.1
3D copper TSV integration, testing and reliability

Tags: IBM, IEDM, TSV

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