FD-SOI and finfets.
There are three reasons why FD-SOI is a better way to go than finfet, says Horacio Mendez, director of the SOI consortium.
The first is obvious: “You can’t say a 3D transistor is cheaper or easier to manufacture than a planar transistor.”
Secondly: “You can port the IP easily with FD-SOI.” IP developed for bulk CMOS processes is easily transported to FD-SOI processes.
Thirdly: “Mobile SOCs need multiple threshold voltages. With back-bias means you can change the voltage on demand using FD-SOI. You can’t do back-bias with a finfet. You can get round it in a different way but at a huge price in power and performance.”
“Putting FD-SOI with metal gate last will be an absolutely stunning technology,” says Professor Asen Asenov Professor of Electrical Engineering at Glasgow University who is founder and CEO of the leading statistical variablity company Gold Standard Simulations.
“this technology will be the absolute winner and it also solves the problems at 20nm. If the companies which use it play their cards well, they will have a competitive advantage.”
“In terms of low power, Intel’s ’22nm” (26nm drawn gate length) finfet process has no big advantage compared to Intel’s 32nm bulk process,” says Asenov. There are, of course, advantages derived from the shrink, but little apparent advantage from the fin.
Intel’s finfet process is “a complex, a very complex process,” says Mendez, “it is difficult to get the same level of yield on a finfet process that you get on a planar process.”
Jean-Marc Chery, CTO and CMO at STMicroelectronics, says that ST’s metal gate first 28nm FD-SOI process delivered: “An ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V.”