Finfets take chips through geometry barrier

The next challenge in semiconductor design is the 14nm process node, and it will be powered by a new type 3D transistor technology transistor, the FinFET, writes Chi-Ping Hsu of Cadence Design Systems

In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor’s elevated channel or “fin”. This approach provides much more control over current compared to planar or flat transistors.

With the promise of a significant reduction in power consumption at a given level of performance, there’s much to like about FinFETs. But they also present real design challenges and tool requirements.

The costs behind moving to 14-nm processes present a huge need to design right first and take a 360-level view when dealing with advanced lithography at an atomic level.

In October, 14nm FinFET technology moved even closer to reality at the ARM TechCon conference, where Cadence announced a 14nm test chip tapeout using the ARM Cortex-M0 processor and IBM’s FinFET process technology. The 14-nanometer ecosystem and chip are significant milestones of a multi-year agreement between ARM, Cadence and IBM to develop systems-on-chip (SoCs) at the advanced process nodes.

So what are the challenges? While digital designers will see little change in their design flows from FinFETs – aside from better performance and lower power – custom/analog designers will face new challenges.

Physical design tools are being changed to support new rules for 14nm and to support new standard cell architectures. Poly gates and fins are new fabric elements that need to be constructed using 14nm rules to create functional standard cells.

One constraint custom designers will face is that all the fins on the transistors on a given chip must be the same width and height. Designers can add fins to increase the width, but this can only be done in discrete increments – you can add 2 fins or 3 fins, but not 2.75 fins.

In this respect there’s less control over the design than with planar transistors, which can be adjusted to arbitrary channel widths. On the tool side, transistor-level extraction must be aware of the capacitance and resistance that arises from the 3D transistor structures. FinFET SPICE models are needed, and they will have additional parameters such as the number of fins. Simulators and layout tools must be able to interpret these models and run in a reasonable period of time.

Like any new semiconductor technology, FinFETs will require an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration between EDA vendors, IP providers, foundries, and semiconductor companies will be crucial. In the coming year Cadence will continue actively working with its partners on EDA support, SPICE models, and test chips for next generation SoCs for 14 nanometers and beyond.

Author is Chi-Ping Hsu, senior v-p R&D, Silicon Realisation Group, Cadence Design Systems