IBM and ARM lead way for very low power SOI chips
IBM and ARM are leading a group of semiconductor companies developing plans to port bulk CMOS designs to fabricate ICs on fully depleted silicon-on-insulator (FD-SOI) substrates.
With ultra-thin buried oxide layers, these devices will offer improved performance and lower operating power.
The companies involved in this collaborative research effort include SOI Industry Consortium members ARM, Leti, Université Catholique de Louvain (UCL), IBM, GlobalFoundries and Soitec.
“This work shows that porting circuits from bulk silicon to FD-SOI can be very direct, depending on the FD-SOI technology used by a specific chipmaker,” said Horacio Mendez, executive director of the SOI Industry Consortium.
“Design porting can enable shorter time-to-market for FD-SOI-based devices. Porting existing bulk CMOS designs to FD-SOI will lead to further optimization of ICs at the 20nm node and even faster implementation of FD-SOI devices.”
The research, which examined both bulk-to-FD-SOI IP porting and full-chip design porting, determined that using existing planar designs with minimal adjustments is especially viable for standard cell libraries, memory compilers and most I/Os, with slightly more efforts for some types of analog and mixed-signal designs.
A design feature of FD-SOI is its potential to operate complete IP cores or full chips at very low supply voltages down to 0.5-0.6V.
The group is examining two paths for full-chip design porting. The most straightforward and fastest porting from bulk silicon to FD-SOI aims at not changing the place-and-route and modifying as little as possible the graphic database system (GDS) contents.
The second approach optimizes the system-on-chip (SOC) design to take full advantage of FD-SOI enhancements such as back-biasing.